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VSC6424QW 参数 Datasheet PDF下载

VSC6424QW图片预览
型号: VSC6424QW
PDF下载: 下载PDF文件 查看货源
内容描述: [Video Shift Register, 10-Bit, CMOS, PQFP128, 14 X 20 MM, PLASTIC, QFP-128]
分类和应用: 外围集成电路
文件页数/大小: 18 页 / 364 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Datasheet  
500 Mb/s Video  
Shift Register IC  
VSC6424  
Package Pin Descriptions  
Table 10: Package Pin Identification  
Signal  
Pin  
I/O Level  
Description  
0V Ground Connection.  
7, 9, 18, 30, 32, 44, 45,58, 59,  
71, 72, 73, 82, 85, 94, 96, 108,  
109, 122, 123  
VCC  
VTT  
VTTL  
3, 6, 13, 26, 33, 70, 77, 90, 97  
-2V Supply Connection.  
+3.3V Supply Connection  
5, 8, 21, 31, 34, 48, 55, 69, 95,  
98, 112, 119  
VREF  
4
-1.32V external ECL Reference voltage.  
The 10 Demultiplexer High-Speed Inputs.  
The 8 Multiplexer High-Speed Outputs.  
101, 102, 103, 104, 105, 68, 67,  
66, 65, 64  
DIN<0:9>  
DOUT<0:7>  
I
ECL  
ECL  
86, 84, 83, 81, 80, 76, 75, 74  
O
89, 91, 92, 93, 110, 111, 113,  
114, 115, 116, 117, 118, 120,  
121, 10, 11, 12, 14, 15, 16, 17,  
19, 20, 22, 23, 24, 25, 27, 28,  
29, 46, 47, 49, 50, 51, 52, 53,  
54, 56, 57  
Slow Bidirectional Bus. Multiplexer Input,  
Demultiplexer Output.  
SB<0:39>  
B
TTL  
MODE  
62  
I
I
TTL  
TTL  
Mux/DMux select signal. 1 for DMUX, 0 for MUX.  
Address enable. In Mux mode, while AEN is low, the  
clock transfers A<0:4> to DOUT<0,2,4,6,7>. In  
DMUX mode it provides retimer input.  
AEN  
RETIME  
100  
CLK  
CLKN  
S<0:2>  
60  
61  
I
I
I
ECL  
ECL  
TTL  
Differential Clock Input (True)  
Differential Clock Input (Complement)  
Shift Register Modulus Control  
39, 40, 41  
Low Speed Clock. Clock used for latching the low  
speed bus in internal timing mode.  
CLKE  
87  
O
ECL  
CLKT  
88  
O
I
TTL  
TTL  
Low Speed Clock. TTL version of above.  
SP<0:2>  
36, 37, 38  
Phase select for output clocks (CLKE, CLKT)  
Shift register load control. Used to transfer data from  
input latch to shift register in external timing mode.  
Data is transferred on the rising edge of CLK while  
SLDN is low. In internal timing mode, SYNC is the  
synchronization input.  
SYNC  
SLDN  
106  
I
TTL  
Input latch control. In external timing mode, LLDN  
low makes the low speed input latches transparent.  
LLDN  
SIN  
43  
42  
I
I
TTL  
ECL  
Serial data in. The shift register can be serially loaded  
using this pin. The data is latched on rising edge of  
CLK. Connect to VTT if not used.  
G52236-0, Rev 3.0  
7/13/99  
VITESSE SEMICONDUCTOR CORPORATION  
Page 15  
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896  
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