VSC6134
Datasheet
2.7.9
Test Error Injection
This block inserts errors into the FEC frame for test purposes. Error insertion is enabled using the active
high configuration bit ERROR_ENA. Bit/burst errors can be optionally selected using the configuration
bits ERRORTYPE[3:0] as shown in the following table. All bits of an error byte are inverted and the
error bytes are consecutive.
Table 40. FEC Error Generator Choices
ERRORTYPE[3:0]
0000
Types of Errors
1 bit error
0001
1 byte error
2 byte errors
3 byte errors
4 byte errors
5 byte errors
6 byte errors
7 byte errors
8 byte errors
Reserved
0010
0011
0100
0101
0110
0111
1000
Others
Two 16-bit configuration registers, ERRFREQ0 and ERRFREQ1, are used to load a 32-bit counter with
a programmable count. When enabled using ERROR_ENA = 1, the counter starts counting down until
reaching zero, at which time a bit/burst error is inserted depending on the ERRORTYPE[3:0] setting.
The counter is then reloaded with the programmed value and starts counting down. Errors are inserted
each time the count reaches zero. Error insertion is disabled if the 32-bit registers are programmed to all
zeros.
Since the internal bus width is 64 bits, the highest and lowest BERs achievable are approximately
–2
–12
1.56 × 10 and 3.64 × 10 , respectively, when ERROR_SEL[3:0] is set to 0000.
The test error generator block I/O descriptions are shown in the following table.
Table 41. Test Error Generator Block I/O Description
Name
Direction
Function
reset_n
IN
IN
Active low reset
Transmit clock
Error enable
Error type
tx_clk
errena
IN
errtype[3:0]
errfreq[31:0]
errdin[63:0]
errdout[63:0]
IN
IN
Error frequency
Data in
IN
OUT
Data out
104 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
