VSC6134
Datasheet
The following figure shows the BCH encoder block diagram.
Figure 19. BCH Encoder Block Diagram
(Message)
(Parity)
Align/
Pack
BCH Encoder
Pack
Polynomial Divider
2.7.8
FEC Scrambler
This block scrambles the 64-bit wide FEC encoded data words using a frame synchronous scrambler
3
12
16
7
with a G.709 generating polynomial 1 + x + x + x + x or G.975 polynomial 1 + x + x . The entire
OTUk or SFEC frames, except for the six framing bytes, are scrambled. The scrambler is reset to FFFF
(hex) all ones on the first bit (MSB) that follows the last framing byte in the FEC frame (that is, the
MSB of the MFAS byte). The scrambler is disabled (data is passed through the block transparently)
when the configuration control bit FECENC_SCRENA is set to 0.
The scrambler block I/O descriptions are shown in the following table.
Table 39. FEC Scrambler Block I/O Description
Name
Direction
Function
reset_n
clock
in
in
in
in
in
Active low reset.
Transmit clock.
Data in.
datai[63:0]
screna
Scrambler enable.
g975_scr
G.975 scrambling enable allows for the use of the G.975 scrambling
PN sequence rather than the G.709 PN sequence for scrambling.
framestart
in
Frame start is aligned with the first word of the OTUk frame.
Data out.
datao[63:0]
out
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
