VSC6134
Datasheet
3.7.9
RLL Justification Interval Register......................................................................... 279
3.7.10 RLL Justification Reversal Direction Register ....................................................... 279
3.7.11 VCO Mode Control Register.................................................................................. 279
Digital Wrapper Overhead Processor and FEC Performance Monitor Registers ............... 280
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
Drop Decoder Bit Error Interrupt Mask Register ................................................... 280
Drop Decoder Bit Error Status Register ................................................................ 280
Add Decoder Bit Error Interrupt Mask Register..................................................... 281
Add Decoder Bit Error Status Register.................................................................. 281
DW Overhead Monitor Interrupt Mask Register 0 ................................................. 282
DW Overhead Monitor Status Register 0.............................................................. 282
DW Overhead Monitor Interrupt Mask Register 1 ................................................. 284
DW Overhead Monitor Status Register 1.............................................................. 284
DW Section Monitor Interrupt Mask Register........................................................ 286
3.8.10 DW Section Monitor Status Register..................................................................... 286
3.8.11 DW TCM Monitor Interrupt Mask Register ............................................................ 288
3.8.12 DW Tandem Connection Monitor Status Register ................................................ 289
3.8.13 DW Tandem Connection Monitor and Path Monitor Interrupt Mask Register ....... 290
3.8.14 DW Tandem Connection Monitor and Path Monitor Status Register.................... 291
3.8.15 DW Path Monitor Interrupt Mask Register............................................................. 292
3.8.16 DW Path Monitor Status Register ......................................................................... 293
3.8.17 DW Overhead Configuration Register 0................................................................ 294
3.8.18 DW Overhead Configuration Register 1................................................................ 294
3.8.19 Standard FEC Uncorrectable Code Word Count (LSW) ....................................... 295
3.8.20 Standard FEC Uncorrectable Code Word Count (MSW) ...................................... 295
3.8.21 Standard FEC Opposite Surround Bit Error Count (LSW) .................................... 295
3.8.22 Standard FEC Opposite Surround Bit Error Count (MSW) ................................... 296
3.8.23 Standard FEC Same Surround Bit Error Count (LSW) ......................................... 296
3.8.24 Standard FEC Same Surround Bit Error Count (MSW) ........................................ 296
3.8.25 Standard FEC Corrected Bit Error Count (LSW)................................................... 297
3.8.26 Standard FEC Corrected Bit Error Count (MSW).................................................. 297
3.8.27 Standard FEC Early Transition Bit Error Count (LSW).......................................... 297
3.8.28 Standard FEC Early Transition Bit Error Count (MSW)......................................... 298
3.8.29 Standard FEC Late Transition Bit Error Count (LSW)........................................... 298
3.8.30 Standard FEC Late Transition Bit Error Count (MSW).......................................... 298
3.8.31 Standard FEC Corrected Symbol (Byte) Error Count (LSW) ................................ 299
3.8.32 Standard FEC Corrected Symbol (Byte) Error Count (MSW) ............................... 299
3.8.33 DW Overhead Monitor APS/PCC Register (MSW) ............................................... 299
3.8.34 DW Overhead Monitor APS/PCC Register (LSW) ................................................ 299
3.8.35 DW Overhead Monitor FTFL Configuration Register ............................................ 300
3.8.36 DW Overhead Monitor FTFL FIFO Access Register............................................. 301
3.8.37 DW Overhead Monitor GCC Configuration Register 1.......................................... 302
3.8.38 DW Overhead Monitor GCC FIFO Access Register ............................................. 302
3.8.39 DW Overhead Monitor Configuration Register...................................................... 303
3.8.40 DW Section Monitor TTI FIFO Register ................................................................ 304
3.8.41 DW Section Monitor Configuration Register.......................................................... 304
3.8.42 DW Section Monitor BIP-8 Bit Error Count Register (MSW)................................. 305
3.8.43 DW Section Monitor BIP-8 Bit Error Count Register (LSW).................................. 305
3.8.44 DW Section Monitor BIP-8 Block Error Count Register (MSW) ............................ 305
3.8.45 DW Section Monitor BIP-8 Block Error Count Register (LSW) ............................. 306
3.8.46 DW Section Monitor BEI Count Register (MSW) .................................................. 306
3.8.47 DW Section Monitor BEI Count Register (LSW) ................................................... 306
9 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
