VSC6134
Datasheet
2.13
2.14
SerDes Interface and Clock Generation ............................................................................. 146
2.13.1 Deserializer Overview ........................................................................................... 146
2.13.2 Serializer Overview ............................................................................................... 146
Programmable PRBS Generator and Checker ................................................................... 148
2.14.1 PRBS Generator (PRBSGEN) .............................................................................. 149
2.14.2 PRBS Checker Monitor Operation ........................................................................ 150
2.14.3 Programmable PRBS Generator and Checker Register Information.................... 151
Operational Modes.............................................................................................................. 152
2.15.1 Operational Mode Descriptions............................................................................. 152
2.15.2 SONET/CBR10G to Line FEC Modes................................................................... 153
2.15.3 10 GbE/Transparent to Line FEC Modes.............................................................. 154
2.15.4 FEC Bridge Modes................................................................................................ 155
2.15.5 FEC Bridge with On-Chip DWOH Processing Modes........................................... 156
2.15.6 FEC Bridge with On-Chip SONET Regeneration Modes ...................................... 157
2.15.7 StFEC(S) <-SONET(Regen) <-Async-> LFEC(S)................................................. 158
2.15.8 FEC to Legacy FEC with Synchronously Mapped Payload Modes....................... 159
2.15.9 StFEC(NS) <-Transparent/SONET <-Async-> LFEC(S)....................................... 160
2.15.10 Complete Device Bypass Modes .......................................................................... 161
2.15.11 SONET <-SONET(Regen)-> SONET, 1/1............................................................. 162
2.15.12 StFEC <-DWOH-> LFEC, 1/1................................................................................ 163
2.15.13 Line FEC Regenerator Loopback Modes.............................................................. 164
2.15.14 Client and Line Interface Card Loopback Modes .................................................. 165
2.15.15 Client-Side Mid-Chip Loopback with Clock Management ..................................... 166
2.15.16 Top-Level Muxes and Mode Configurations.......................................................... 166
2.15.17 Protection Switching Mode.................................................................................... 168
2.15.18 Operational Modes Register Information............................................................... 172
Microprocessor Interface Description.................................................................................. 173
2.16.1 External Microprocessor Modes and Timing......................................................... 173
2.16.2 Configuration Bits.................................................................................................. 174
2.16.3 Motorola Processors ............................................................................................. 174
2.16.3.1 Motorola Pseudo-Synchronous Mode...................................................... 175
2.16.3.2 Motorola Synchronous Mode................................................................... 179
2.16.4 Intel Processors..................................................................................................... 183
2.16.4.1 Intel Synchronous Mode .......................................................................... 183
2.16.4.2 Intel Asynchronous Mode ........................................................................ 186
Special Topics..................................................................................................................... 191
2.17.1 Device Initialization (Reset)................................................................................... 191
2.17.2 Status/Interrupt Handler Protocol.......................................................................... 193
2.17.3 Performance Monitor One-Second Pulse.............................................................. 195
2.17.4 Loss of Input Clock (LOCK) Monitor...................................................................... 196
2.17.5 VSC6134 Clocking Structure................................................................................. 197
2.17.6 JTAG Block Functional Description....................................................................... 197
2.17.7 Word Swap Function............................................................................................. 198
2.15
2.16
2.17
3
Registers......................................................................................................................................... 201
3.1
Register Summary .............................................................................................................. 201
3.2
Line Overhead Monitor Registers ....................................................................................... 226
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
LOHM Line DCC Message Registers.................................................................... 226
LOHM Configuration Register ............................................................................... 226
LOHM Interrupt Mask Register.............................................................................. 227
LOHM Interrupt Status Register............................................................................ 229
LOHM BIP-8 Bit Error Counter (MSW) Register ................................................... 230
6 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
