VSC6134
Datasheet
2.10
10-GbE Receiver Monitor
The XGE_RX block has three major components: PCS, MAC, and MPUIF_MIB blocks. The
block-level top I/O descriptions are given in the following table.
Table 56. XGE_RX I/O Description
Name
Direction
IN
Function
RESET_N
Active low reset
CLK_161
IN
161.1328125 MHz PCS clock
PCS data input
DATA_IN[63:0]
MPU_RESETN
MPU_CLK
IN
IN
Active low MPU_CLK reset
Microprocessor clock
IN
MPU_SEL
IN
Microprocessor block select signal
Microprocessor read enable signal
Microprocessor write enable signal
Microprocessor address bus
Microprocessor write data bus
Microprocessor block interrupt
Microprocessor read data bus
Microprocessor data acknowledgement pulse
MPU_RDENA
MPU_WRENA
MPU_ADDR[6:0]
MPU_WDATA[15:0]
MAC_INT
IN
IN
IN
IN
OUT
OUT
OUT
MAC_RDATA [15:0]
MAC_DTK
2.10.1
10-GbE MPU Interface and MIB/RMON Block
The minimum microprocessor speed is expected to be 15 MHz. After an interrupt is generated by any
status bit in MIB/RMON Counters Saturate/Rollover Status Register 0 and MIB/RMON Counters
Saturate/Rollover Status Register 1, any further interrupts from this bit within a few minutes of the
initial interrupt should be ignored because it takes more than 57 minutes to saturate and roll over the
counters again to produce a new valid interrupt. For more information, see “MIB/RMON Counters
Saturate/Rollover Status Register 0,” page 324 and “MIB/RMON Counters Saturate/Rollover Status
Register 1,” page 326.
The hash table configuration registers are used for programming of acceptable multicast addresses.
There are four hash table configuration registers: HASH1, HASH2, HASH3, and HASH4. Each bit in
the hash table registers refers to a 6-bit value that is generated by XORing the 8 bits of the lower 5 bytes
and the 6 (LSB) bits of the upper byte of a 6-byte destination address. This results in 64 possible values
that can be represented by the 6-bit value generated by the XORing.
138 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
