VSC3138
Datasheet
DRIVE Input
Downloaded by pm_virendrakumar@yahoo.com on January 18, 2007 from Vitesse.com
The VSC3138 provides a DRIVE input that can be connected internally to any of the device’s 40 data input connections.
By connecting an external signal to the DRIVE input and then switching it to one of the 40 data inputs, a test signal can be
placed on that input.
The signal from the DRIVE input is superimposed onto the data input path, rather than multiplexed between the DRIVE
and data input signals. This is done so that the DRIVE input can be used to verify signal path integrity. For correct
operation, the signal present on the selected input must be either in a neutral state or in a high-impedance state to allow the
DRIVE input to have an effect on the data input under test.
The DRIVE input can also be used with the SENSE output and an external test generator/receiver to verify programmed
signal path integrity.
The DRIVE input can be programmed to drive any or all of the 40 data inputs. Writing to the appropriate address either
connects or disconnects a data input from the specified DRIVE input.
SENSE Output
The VSC3138 provides a SENSE output that can be used to monitor any one of the 40 data outputs. The SENSE output
monitors the data output signal at the package pin, thereby facilitating true verification of the complete signal path
through the switch.
The SENSE output can be used with the external monitoring circuit and DRIVE input to determine the presence of a
signal on any output or to determine signal path integrity.
PRBS Control
The Pseudo-Random Bit Sequence (PRBS) Generator and Detector can generate and detect four NRZ patterns: 2
7
-1, 2
9
-
1, 2
10
-1, and 2
11
-1. The main purpose of the PRBS Generator and Detector is to provide for switch diagnostics and signal
tracing functions. The block diagram of the PRBS Generator is shown in
and Detector is determined by the external clock signal to a maximum of 400 Mbps. The PRBS output data is clocked on
the rising edge of the clock. The PRBS function controls are located in the PRBS Generator Configuration register
0x284’h. The PRBS Generator is enabled by writing 1 to the PRBS Generator Enable bit [4] of the PRBS Generator
Configuration register. Pattern length is selected using the PRBS Generator Pattern Length Selection bits [3] and [2] of
the PRBS Generator Configuration register. Selecting 00 will generate pattern 2
7
-1, 01=2
9
-1, 10=2
10
-1, 11=2
11
-1. It is
possible to invert the pattern by writing 1 into the PRBS Output Invert bit [1] of the PRBS Generator Configuration
register.
The PRBS Detector uses the same clock as the PRBS Generator. The block diagram of the PRBS Detector is shown in
PRBS Generator Configuration register to 1. It may be necessary to invert the Detector’s clock in order to compensate for
the phase difference between the PRBS data input and the clock. The PRBS Detector is enabled by writing a 1 to the
PRBS Input Pattern bit [4] of the PRBS Detector Configuration register. The Detector pattern length is selected by the
Detector Pattern Length Select bits [6] and [5] of the PRBS Detector Configuration register. Respectively; 00 represents
pattern 2
7
-1, 01=2
9
-1, 10=2
10
-1, 11=2
11
-1. The error counter is not enabled until the pattern detector recognizes the
pattern coming into the detector. It can take up to 30 clock cycles for the detector to recognize the pattern. Once the
pattern has been detected, the PRBS Lock Detect bit [2] of the PRBS Error Status register (address 288’h) goes HIGH.
5 of 44
G52414 Revision 4.2
March 8, 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
