VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.5 Gb/s 16-Bit Multiplexer/
Demultiplexer Chipset
VSC8061/VSC8062
VS8061 Phase Detector Logic Diagram
The phase detector inside the VS8061 compares the phase difference between the internally generated
divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in phase,
the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses with pulse
widths proportional to the phase difference will be present at the U output. Conversely, if DCLK precedes
CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D output.
The other output will remain low. The Phase Detector ignores phase differences for falling edges. This circuitry
is useful for implementing a Clock Multiplier Unit (CMU) function with the VS8061. For example, the DLCK
can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator (VCO) at
16X the frequency of the reference clock can be used as the CLK input for the VS8061. The phase detector out-
puts (U and D) can then be used by an external integrator to generate an output that controls the VCO. The gen-
erated 16X clock from the VCO will be phase-locked to the reference clock.
Figure 4: VS8061 Phase Detector Logic Diagram
U
CLK16
R
S
Q
Q
S
R
DCLK
D
Figure 5: Phase Detector Input and Output Waveforms
CLK16
DCLK
U
D
Page 4
VITESSE SEMICONDUCTOR CORPORATION
G52069-0, Rev. 4.1
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
6/22/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
