VS8004/8005
VITESSE
Data Sheet
2.5 Gbits/sec 4-Bit Multiplexer/
Demultiplexer Chipset
Table 4: High Speed Outputs
(Over recommended operating conditions, V
CC
= GND, Output load = 50
Ω
to -2.0V)
Parameter
V
OH
V
OL
∆V
OUT
Description
Output HIGH voltage
Output LOW voltage
Output voltage swing
Min
-
-
0.8
Typ
-0.9
-1.8
1.0
Max
-
-
1.4
Units
V
V
V
Conditions
Terminated to -2.0V through 50Ω
Terminated to -2.0V through 50Ω
Output Load, 50Ω to -2V
Notes: 1) ESD protection is not provided for the high speed input pins, therefore, proper procedures should be used when handling
Parallel Data, CLK, NCLK, SKIP, NSKIP Inputs
ECL inputs (clock or data) provide for AC coupled operation. Internal biasing will position the reference
voltage of approximately -1.32 Volts on both the true and complement inputs.
Chip Boundary
V
CC
= GND
0.1
µF
-1.32V
-1.32V
50Ω
0.1
µF
RII = 1KΩ
V
TT
V
TT
V
TT
= -2V
High Speed Inputs
High speed inputs (clock or data) provide for AC coupled operation. Internal biasing will position the refer-
ence voltage of approximately -3.5 Volts on both the true and complementary inputs. Single-ended, AC coupled
operation is illustrated below
.
Chip Boundary
V
CC
= GND
150 pF
-3.5V
-3.5V
50Ω
150 pF
RII = 1KΩ
V
TT
V
TT
V
EE
= -5.2V
V
TT
= V
CC
-2V
Page 8
®
VITESSE
Semiconductor Corporation
G52012-0 Rev. 2.0
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
