VS8004/8005
VITESSE
Data Sheet
2.5 Gbits/sec 4-Bit Multiplexer/
Demultiplexer Chipset
Figure 6: VS8005 Pin Diagram
D
DN2
D
VC
N
D
NDØ
14 13 12 11 10
9
8
15
16
17
18
19
20
21
ND3
VCCA
CLK4
NCLK4
VEE
7
6
5
4
DØ
VCCA
VEE
VS8005
Heat Sink
Side
VCC
VEE
3
2
VCC
VCC
NSKIP
NC
1
22 23 24 25 26 27 28
CN
EV
LCK
KSIP
CNLK
DSTA
SNTDA
Table 6:VS8005 Pin Description
Pin #
Name
I/O
Description
24, 23
26, 27
CLK, NCLK
SDATA, NSDATA
CLK4, NCLK4
D( :3), ND( :3)
SKIP, NSKIP
VEE
I
I
Differential high speed clock inputs
Differential high speed serial data outputs
Differential divide by 4 clock outputs (ECL)
Differential parallel data outputs (ECL)
Differential word boundary inputs (ECL)
-5.2V supply voltage
17, 18
O
O
I
7-10, 12-15
28, 1
3, 5, 19, 25
2, 4, 11, 20
6, 16
VCC
V ground connection
VCCA
V output ground connection
21, 22
NC
No connection
Notes: 1) The heat sink is connected to VEE (pin 25). To prevent a short circuit between VCC, VCCA
mally), do not connect this heat sink to ground.
(
V normally) and VEE (-5.2V nor-
2) The falling edge of SKIP causes realignment of the parallel word boundary making parallel data invalid for three CLK4,
NCLK4 (12 CLK, NCLK) periods.
Page 10
® VITESSE Semiconductor Corporation
G52012-0 Rev. 2.0
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
