VITESSE
Data Sheet
Features
• Serial Data Rates up to 2.5 Gb/s
• Parallel Data Rates up to 625 Mb/s
• ECL 100K Compatible Parallel Data I/Os
• Divide-by-4 Clock for Synchronization of
Parallel Data to Interfacing Chips
• SKIP Input on Demux for Realignment of
Output Word Boundaries
VS8004/8005
2.5 Gbits/sec 4-Bit Multiplexer/
Demultiplexer Chipset
• Differential or Single-Ended Inputs and Outputs
• Low Power Dissipation: 1.5 W (Typ. Per Chip)
• Standard ECL Power Supply: VEE = -5.2 V
• Available in Commercial (0
°
to +70°C) or Indus-
trial (-40° to +85°C) Temperature Ranges
• Proven E/D Mode GaAs Technology
• 28-pin Leaded Ceramic Chip Carrier
Functional Description
The VS8004 and VS8005 are data conversion devices capable of serial data rates up to 2.5 Gb/s, transform-
ing 4-bit wide parallel data to serial data and serial data to 4-bit wide parallel data.
The VS8004/VS8005 are fabricated in gallium arsenide using the Vitesse H-GaAs™ E/D MESFET process
which achieves high speed and low power dissipation. These products are packaged in a ceramic 28-pin leaded
chip carrier.
VS8004
The VS8004 is a high speed 4 bit parallel to serial data converter suitable for digital voice or data communi-
cations applications. All inputs and outputs can be used differentially or single-ended. The parallel inputs
[D(0:3), ND(0:3)] accept data at rates up to 625 Mb/s. The differential serial data output (SDATA, NSDATA)
presents the data sequentially from the parallel data inputs at rates up to 2.5 Gb/s, synchronous with the differ-
ential high speed clock input (CLK, NCLK). An internal timing generator receives the high speed clock input
and divides it by four to create a differential clock output (CLK4, NCLK4). This clock signal is provided so that
incoming parallel signals can be synchronized to arrive at the input data registers simultaneously. An internal
bias network is provided at all inputs to simplify capacitive coupling.
VS8005
The VS8005 is a high speed 4-bit serial to parallel data converter suitable for digital voice or data commu-
nications applications. All inputs and outputs can be used differentially or single-ended. The differential serial
data inputs (SDATA, NSDATA) accept data at rates up to 2.5 Gb/s, synchronous with the differential high speed
clock input (CLK, NCLK). The parallel outputs [D(0:3), ND(0:3)] present the data sequentially at rates up to
625 Mb/s. An internal timing generator receives the high speed clock input and divides it by four to create a dif-
ferential clock output (CLK4, NCLK4) which is synchronous with the parallel data outputs. A control input
(SKIP, NSKIP) is provided to allow realignment of the output parallel word boundaries.
SKIP Signal
The SKIP signal is provided to allow realignment of the output parallel 4-bit word boundaries. Within the
current CLK4, the rising edge of a SKIP causes an internal circuit in the VS8005 to hold the current 4-bit word
output and drop the fifth output bit. The sixth output bit will become the MSB of the next 4-bit word output; and
G52012-0 Rev. 2.0
®
VITESSE
Semiconductor Corporation
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VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
