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DCM4623TC8G16F0T00 参数 Datasheet PDF下载

DCM4623TC8G16F0T00图片预览
型号: DCM4623TC8G16F0T00
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Control 3623 and 4623 ChiP DCMs Evaluation Board]
分类和应用:
文件页数/大小: 17 页 / 542 K
品牌: VICOR [ VICOR CORPORATION ]
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Trim Control  
nJumper block J09 configures trimming.  
nWith no jumpers installed, neither the trim potentiometer nor the test point for external trim con-  
trol is connected to the TR net. Note that the paralleling connectors always connect to the TR net.  
nWith a jumper loaded across J09.1 and J09.2, the trim potentiometer R26 is  
connected as a rheostat between the TR node and SG.  
nWith a jumper loaded across J09.3 and J09.4, the external trim test point is  
connected to the TR node.  
nThe DCM contains an internal pull-up resistor to VCC (3.3V nominal). When VIN is applied to the DCM  
it samples the TR node voltage. If it has pulled up to VCC, the DCM disables trimming as long as it  
has input power, and the programmed trim condition will be nominal rated VOUT of the DCM model.  
nIf the TR node is not permitted to pull-up to VCC when VIN is applied, trimming is enabled for as long  
as the DCM has input power.  
nNote: Any load on the TR node may cause the DCM to select trim mode when VIN is applied,  
including: the external trim testpoint (if selected with the jumper block), the trim potentiometer  
(if selected with the jumper block), and other DCM evaluation boards attached to the  
paralleling connectors.  
nThe trim potentiometer adds a variable resistance between the TR node and SG, from between  
0Ω nominal, to the value of the potentiometer (500kΩ). This resistance range will generate TR pin  
voltages which cover the entire functional range of the TR pin. Care should be taken to ensure the  
programmed trim condition is within the rated trim range of the DCM in order for the DCM to meet  
specifications.  
nIn a parallel setup using the J02 & J03 paralleling connectors, all boards besides the top one should  
have the trim jumper select block at J09 open.  
nIn a parallel setup with multiple DCM evaluation boards, each DCM contributes another internal  
pull-up resistor to a 3.3V nominal rail. With any resistive based trimming of the TR node, the resultant  
trim condition will be modified by the number of DCMs which are attached and have VIN applied.  
Conversely with a voltage source applied to the TR node, adding additional DCMs to the system has  
minimal impact on the resultant trim condition.  
Fault Monitoring  
nJumper block J10 configures how the FT node is monitored.  
nWith no jumpers installed, neither the visible LED nor the opto-coupler is connected to the FT net.  
Note that the paralleling connectors always connect to the FT net.  
nWith a jumper loaded across J10.3 and J10.4, the visible LED at D01 and its bias resistor network  
R09 & R32 are connected to the FT node.  
nWith a jumper loaded across J10.1 and J10.2, the opto-coupler at M02 and its bias resistor net-  
work R21 & R22 is connected to the FT node.  
nThe DCM FT output is intended to be directly paralleled with the FT output of other DCMs in an array.  
The FT node in an array forms a “wired-OR”, where any DCM can drive the FT node high.  
UG:017  
vicorpower.com  
Applications Engineering: 800 927.9474  
Page 15  
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