CHU3377
Typical Assembly and Bias Configuration
DC lines
-V
+V
W-band Multiplier/MPA
>= 47pF
>= 47pF
L_in
L_out
µ-strip line
µ-strip line
This drawing shows an example of assembly and bias configuration. All the transistors
are internally self biased. An external chip capacitor of at least 47pF is necessary for the
positive and negative supply voltages.
For the RF pads the equivalent wire bonding inductance (diameter=25µm) have to be
according to the following recommendation.
Pin name
IN
OUT
Equivalent inductance
L_in
≤
0.3 nH
L_out
≤
0.15 nH
(2)
Wire length (1)
≤
0.4 mm
0.2 mm
(2)
(1) This value is the total length including the necessary loop from pad to pad.
(2) For longer wire length or higher inductance, an external compensation is
required to match 50Ω between OUT Pin and 0.15nH wire inductance plan. (For
Ω
example with a matching network on the substrate)
Chip backside must be RF grounded.
Ref.: DSCHU33777082 - 23 Mar 07
4/6
Specifications subject to change without notice
Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE
Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
