CHR0100a
Typical Bias Configuration
5.8GHz Image rejection mixer
The typical bias voltage applied to the chip is Vd = 4V.
If the LO power is low (ex: < 5dBm) one can apply a negative voltage (-0.3V) on
Vg to improve and secure the conversion characteristic.
Each Vg and Vd port should have a 10nF decoupling capacitor to the ground.
Connection of only one of the two VgQ and Q pads is necessary
VgI
10nF
VgQ
10nF
I
Q
Vd
10nF
LO
CHR0100a
RF
10nF
VgQ
Q
Chip Mechanical Data
CHR0100a
Chip size 1770
±
20 µm x 1370
±
20 µm
Chip thickness 100
±
10 µm
Ref. : DSCHR01000161 -9-Jun-00
4/6
Specifications subject to change without notice
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