CHA3666
Chip Biasing options
6-17GHz Low Noise Amplifier
This chip is self-biased, and flexibility is provided by the access to number of pads. The
internal DC electrical schematic is given in order to use these pads in a safe way.
Vd1
1.5K
40
3.1K
Vd2
0.3K
0.3K
2.5
RFin
90
90
20
20
8
RFout
P1
Two standard biasing :
Low Noise and low consumption :
P2
N2
Vd1=Vd2 = 4V and P1, N2 grounded.
P2 pads non connected ( NC).
Idd = 80mA & Pout-1dB = 17dBm Typical.
Vd1=Vd2 = 4V and P1, P2 grounded.
N2 pads non connected ( NC).
Idd = 85mA & Pout-1dB = 17.5dBm Typical.
Low Noise and higher output power
Ordering Information
Chip form :
CHA3666-99F/00
Information furnished is believed to be accurate and reliable. However
United Monolithic Semiconductors
S.A.S.
assumes no responsability for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of
United Monolithic Semiconductors S.A.S..
Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied.
United Monolithic Semiconductors S.A.S.
products are not authorised for use
as critical components in life support devices or systems without express written approval from
United Monolithic
Semiconductors S.A.S.
Ref. : DSCHA36666159 - 08 Jun 06
8/8
Specifications subject to change without notice
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UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
