36-44GHz Low Noise Amplifier
Chip Biasing options
CHA2194
Internal DC schematic
This chip is self-biased, and flexibility is provided by the access to positive Vg.
The internal DC electrical schematic is given in order to use these pads in a safe way.
Absolute recommandations:
N°1 : Do not exceed Vds* = 3,5 Volt ( internal Drain to Source voltage ).
N°2 : Do not bias in such a way that Vgs* becomes positive. (:internal Gate to Source
voltage )
Typical biasing table and Typical results in test Jig at 40 GHz
40GHz IN TEST Jig
Standard
Low Noise High linearity
Low noise /low current consumption
Switch off
Vds ( V) Vg12 (V) Vg3 (V)
3.5
4
3,5
3.5
NC
1
-1
-8
NC
1
-1
-5
Id (mA)
42
60
30
0
Typical NF(dB) Typical Gain (dB) Typical P-1dB (dB) Typical Psat (dB)
2.9
2,95
3
X
19
20
17,5
X
10
11
8
X
12
14
11
X
Ref : DSCHA21942035 -04-Feb.-02
9/10
Specifications subject to change without notice
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