GA1087
AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t CPWH
t CPWL
t IR
CLK pulse width HIGH
Figure 4
Figure 4
3
3
---
---
—
—
—
ns
ns
ns
CLK pulse width LOW
Input rise time (0.8 V - 2.0 V)
—
2.0
Symbol Input Clock (Q0–Q10)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t OR,t OF
Rise/fall time (0.8 V – 2.0 V)
Figure 4
350
–850
–1050
—
—
–350
–350
60
1400
+150
+350
150
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
µs
2
t PD1
CLK ↑ to FBIN ↑ (GA1087-MC500)
CLK ↑ to FBIN ↑ (GA1087-MC700)
Rise–rise, fall–fall (within group)
Rise–rise, fall–fall (group-to-group, aligned)
Figure 4
2
t PD2
Figure 4
3
t SKEW1
t SKEW2
t SKEW3
t SKEW4
Figure 5
3
3
3
Figure 6 (skew2 takes into account skew1)
—
75
350
Rise–rise, fall–fall (group-to-group, non-aligned) Figure 7 (skew3 takes into account skews1, 2)
—
—
—
650
Rise–fall, fall–rise
Duty-cycle Variation
Period-to-Period Jitter
Random Jitter
Figure 8 (skew4 takes into account skew3)
—
1200
+1000
200
4
t CYC
Figure 4
Figure 4
Figure 4
–1000
—
0
5
t JP
80
5
t JR
—
190
10
400
6
t SYNC
Synchronization Time
—
500
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because
the input duty cycle can vary.
while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock.
t
JP is the jitter on the output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
Y
+5 V
R1
+5 V
R1
50 Ω
X
Z
+5 V
R1
Q0
Q1
Q2
•
•
•
FBIN
CLK
R2
R2
•
•
•
•
R2
+5 V
R1
+5 V
R1
Z
•
Q10
R2
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y + Z = X
5
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TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
