T
R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
GA1087
FBIN GND REFCLK GND
11
10
9
8
F1
7
F0
6
GND
5
TEST
12
VDD
13
Phase
Detector
VCO
4
VDD
3
2
Q10
Q9
11-Output
Configurable
Clock Buffer
Features
• Wide frequency range:
24 MHz to 105 MHz
• Output configurations:
five outputs at f
REF
five outputs at f
REF
/2 or
six outputs at 2x f
REF
four outputs at f
REF
• Low output-to-output skew:
150 ps (max) within a group
SYSTEM TIMING
PRODUCTS
Q0
14
GND
15
Q1
Q2
16
17
MUX
Divide Logic
÷4, ÷5, or ÷6
Output Buffers
Group B
Group A
1
GND
28
27
Q8
Q7
VDD
18
26
VDD
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint’s GA1087 is a configurable clock buffer which generates 11 outputs,
operating over a wide range of frequencies — from 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and
1
/
2
x the
reference clock frequency, f
REF
. When one of the Group A outputs
(Q5–Q10) is used as feedback to the PLL, all Group A outputs will be at
f
REF
, and all Group B outputs (Q0–Q4) will be at
1
/
2
x f
REF
. When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
will be at 2x f
REF
and all Group B outputs will be at f
REF
.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. Completely self-contained, this PLL requires no external
capacitors or resistors. The PLL’s voltage-controlled oscillator (VCO)
has a frequency range from 280 MHz to 420 MHz. By feeding back one
of the output clocks to FBIN, the PLL continuously maintains frequency
and phase synchronization between the reference clock (REFCLK) and
each of the outputs.
TriQuint’s patented output buffer design delivers a very low output-to-
output skew of 150 ps (max). The GA1087’s symmetrical TTL outputs
are capable of sourcing and sinking 30 mA.
• Near-zero propagation delay:
–350 ps +500 ps (max) or
–350 ps +700 ps (max)
• TTL-compatible with 30 mA
output drive
• 28-pin J-lead
surface-mount package
For additional information and latest specifications, see our website:
www.triquint.com
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