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S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
GA1086
S1
10
CLK
9
S0
8
NC
7
NC
6
GND
5
S2
12
VDD
13
Q/2
14
GND
15
FBOUT
16
Q1
17
Control
Logic
Phase
Detector
VCO
4
VDD
3
2
Q9
Q8
11-Output
Clock Buffer
Features
•
Operates from 30 MHz to 67MHz
•
Pin-to-pin output skew of
250 ps (max)
•
Period-to-period jitter:
75 ps (typ)
•
Near-zero propagation delay:
–350 ps
±
500 ps or
–350 ps
±
1000 ps
•
10 symmetric, TTL-compatible
outputs with 30 mA drive and
rise and fall times of 1.4 ns(max)
SYSTEM TIMING
PRODUCTS
Divide
Logic
MUX
Precision
Output
Buffers
1
GND
28
27
Q7
Q6
VDD
18
26
VDD
19
20
21
22
23
24
25
GND
Q2
Q3
VDD
Q4
Q5
GND
TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock
buffer chip supports the tight timing requirements of high-performance
microprocessors, with near zero input-to-output delay and very low pin-to-
pin skew. The device offers 10 usable outputs synchronized in phase and
frequency to a periodic clock input signal. One of the ten outputs is a one-
half clock output (CLK
÷
2). With split termination, the GA1086 can be
used to drive up to nineteen 15 pF loads, as shown in Figure 10.
The tight control over phase and frequency of the output clocks is achieved
with a 400 MHz internal Phase-Locked Loop (PLL). By feeding back one of
the output clocks to FBIN, the on-chip PLL continuously maintains
synchronization between the input clock (CLK) and all ten outputs. Any
drift or gradual variation in the system clock is matched and tracked at the
ten outputs. The GA1086 output buffers are symmetric, each sourcing and
sinking up to 30 mA of drive current. For diagnostic purposes, the device
has a test mode which is used to test the device and associated logic by
single-stepping through the control logic.
The GA1086 is fabricated using TriQuint’s One-Up™ gallium arsenide
technology to achieve precise timing control and to guarantee 100% TTL
compatibility. The output frequency makes this device ideal for clock
generation and distribution in a wide range of high-performance
microprocessor-based systems. Many other CISC- and RISC-based
systems will also benefit from its tight control of skew and delay.
•
28-pin J-lead surface-mount
package
•
Special test mode
•
Meets or exceeds Pentium
™
processor timing requirements
•
Typical applications include
low-skew clock distribution for:
•
RISC- or CISC-based systems
•
Multi-processor systems
•
High-speed backplanes
For additional information and latest specifications, see our website:
www.triquint.com
1
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