GA1085
AC Characteristics
Symbol
t
CPWH
t
CPWL
t
IR
(V
DD
= +5 V + 5%, T
A
= 0
°
C to +70
°
C)
Test Conditions (Figure 3)
1
Figure 4
Figure 4
Input Clock (REFCLK)
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V – 2.0 V)
Min Typ
3
3
—
---
---
—
Max
—
—
2.0
Unit
ns
ns
ns
Output Clocks (Q0–Q10)
t
OR,
t
OF
t
PD2
t
SKEW13
t
SKEW2
3
Rise/fall time (0.8 V–2.0 V)
CLK Î to FBIN Î (GA1085-MC1000)
Rise–rise, fall–fall (within group)
Rise–rise, fall–fall
(group-to-group, aligned)
Rise–rise, fall–fall
(group-to-group, non-aligned)
Rise–fall, fall–rise
Duty-cycle Variation
Period-to-Period Jitter
Random Jitter
Synchronization Time
Figure 4
Figure 4
Figure 5
Figure 6
(skew2 takes into account skew1)
Figure 7
(skew3 takes into account skew1, skew2)
Figure 8
(skew4 takes into account skew3)
Figure 4
Figure 4
Figure 4
350 — 1400
–1350–350 +650
—
—
—
—
60
75
—
—
150
350
650
1200
+1000
200
400
500
ps
ps
ps
ps
ps
ps
ps
ps
ps
µs
SYSTEM TIMING
SYSTEM TIMING
PRODUCTS
t
SKEW33
t
SKEW43
t
CYC4
t
JP5
t
JR5
t
SYNC6
Notes:
–1000 0
— 80
— 190
— 10
1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay t
PD
is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. t
JR
is the jitter on the output with respect to the reference clock.
t
JP
is the jitter on the output with respect to the output’s previous rising edge.
6. t
SYNC
is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1
R2
Z
FBIN
Q0
Q1
Q2
•
•
•
•
Q10
Y
50
Ω
X
+5 V
R1
R2
•
•
•
•
+5 V
R1
R2
+5 V
R1
R2
Notes:
R1 = 160
Ω
R2 = 71
Ω
Y+Z=X
+5 V
R1
R2
Z
CLK
For additional information and latest specifications, see our website:
www.triquint.com
5
TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
