Tr i path Technol ogy, I nc. -
Technical Information
TLD4012
ADSL LINE DRIVER USING TRIPATH DIGITAL POWER
PROCESSING (DPP™) TECHNOLOGY
Technical Information
Revision 2.0a – May 2002
GENERAL DESCRIPTION
The TLD4012 is an ADSL line driver that provides very low power consumption and
low distortion in a very small package as a result of Tripath’s proprietary power
processing technology. This device accepts differential input signals from an analog
front-end (AFE), and can be used in full-rate (G.dmt), or G.lite systems. This TLD4012
offers a low power consumption of 650mW for full-rate, full-power, CO-side, FDM
(non-overlapped) transmissions.
APPLICATIONS
FEATURES
Full-rate or G.lite line cards
DSLAMs
DLC equipment
Central office switches
BENEFITS
Reduced line card power
Reduced system power
Increased line card density
More ports per cubic foot of system
space
Improved system performance
Simplifies thermal management on
PCB
Improved reliability
Flexible solution
Tripath Proprietary Power Processing technology
Very low power consumption
P
CONS
(Full-rate ADSL) = 650 mW (typ)
P
CONS
(G.lite) = 390 mW (typ)
Low distortion
Spurious free dynamic range = -80 dBc 26kHz to 138kHz,
R
LINE
=100Ω, P
LINE
=19.8dBm
Third harmonic distortion = -83 dBc at f = 100 kHz,
-82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, V
OUT
= 10Vpp
(differential), 70Ω load
500 mA minimum output current into a 71Ω load
Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps)
Low-power mode -130 mW typical (line terminated -allows
reception of incoming signals)
Disabled mode - 10 mW typical (no line termination)
Over-temperature and over-current protection with Fault output
5x5 mm 32-pin TQFP with exposed die pad
AUTO_CLR
VDD5
25
VSS5
16
VDD15
21
VSS15
20
NC
INP 3
Power
Processing
Block
23 OUTP
18 OUTN
EN_AC
GND
INP
INN
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
124
23
22
21
20
19
18
9
17
10 11 12 13 14 15 16
NC
30 FBP
VDD5
GND
FBN
FBP
R
EXT
NC
OUTP
NC
VDD15
VSS15
NC
OUTN
NC
INN 4
29 FBN
G3 9
G2 8
G1 7
G0
RESETB
LOPWR
EN_AC
AUTO_CLR
6
14
15
1
31
GND
G0
G1
FORC_BIAS
RESETB
2
GND
5
GND
28
GND
12
FORC_BIAS
13
TH_FAULT
(Top View)
1
Block Diagram
TLD4012 – JB/Rev. 2.0a/05.02
TH_FAULT
LOPWR
VSS5
FAULT
Control
&
Logic
Output
current
limit
27 R
EXT
11 FAULT
G2
NC
G3