Tripath Technology, Inc. – Preliminary Technical Information
frequency clock (LRCK). In addition, a master clock (MCK) synchronizes all digital operations inside the
device. Each DATAnn input carries serial data for 2 channels. The LRCK clock differentiates between odd
and even channel data. BITCK is synchronized with the serial data input, and latches data on either rising
edges or falling edges of BITCK (programmable option).
The TCD6001 has 3 serial data inputs (DATA12, DATA34, and DATA56) and therefore can receive 6
channels of audio data. The group of bits received on a DATAnn input during a half period of LRCK clock is
called a PCM data sample. It is a 2’s complement representation of the amplitude of sound on that channel
at that time.
There are 32 pulses of BITCK for every half period of LRCK. So, in theory, it is possible to read up to 32 bits
of data per sample. However, only a maximum of 24 bits are read. The device will also accept 16, 18, and
20 bit formats depending on what has been specified in the control registers.
The most significant bit of data always arrives first and the least significant bit last. Data can be left aligned
or right aligned to the LRCK clock. If data is left aligned, the most significant bit of data arrives at the
beginning of the LRCK half-period. If data is right aligned, the least significant bit of data arrives just before
the end of the LRCK half-period.
DW1 and DW0 define the input data width. Any data outside of the selected data width will be ignored.
DW1
DW0
Input Data Width
16 bit
0
0
1
1
0
1
0
1
18 bit
20 bit
24 bit
LRA specifies the left/right data alignment scheme. When LRA is ‘0’, data is left aligned to LRCK transitions.
When LRA is ‘1’, data is right aligned to LRCK transitions.
If data is left aligned, the most significant bit of data can arrive on the first or the second BITCK pulse. The
I2S format specifies that it arrive on the second BITCK pulse. When the I2S control bit is ‘1’, the data
conforms to the I2S standard - the most significant data bit is read during the second BITCK pulse. When
the I2S control bit is ‘0’, the most significant data bit is read during the first BITCK pulse. If data is right
aligned, the I2S control bit has no effect.
When CCK is ‘0’, even channel data (channels 2, 4, and 6) is read while LRCK is high and odd channel data
(channels 1, 3, and 5) is read while LRCK is low. When CCK is ‘1’, odd channel data is read while LRCK is
high and even channel data is read while LRCK is low.
When BCK is ‘1’, data is latched on the falling edge of BITCK. When BCK is ‘0’, data is latched on the rising
edge of BITCK.
DP is used to specify the polarity of the 2’s complement audio data. If DP is ‘0’, the data is non-inverted. If
DP is ‘1’, the data is inverted.
Figure 1 shows several examples of digital input format. Notice that for a given stereo audio sample, the
TCD6001 reads even channels first and then the odd channels. I2S and most of its variations first send left
channel data and then right channel data within stereo audio sample frames. Therefore, the TCD6001 sends
left channel input data to output channels 2, 4 and 6 and right channel input data to output channels 1, 3,
and 5.
Inverting CCK to send left channel data to odd channels can potentially cause phase shift problems. For
example, if standard I2S data is received with register 24h = 0Bh instead of 1Bh, stereo data frames are
read beginning with the rising edge of LRCK instead of the falling edge. This means that left and right
channel data will be out of phase by ½ of a LRCK cycle.
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TCD6001 – JL/Rev. 0.9/07.05
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