Tripath Technology, Inc. – Preliminary Technical Information
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The Sync Reset mode (control bits R0 and R1)
The High Frequency Master Clock option (control bit HFR)
If the Left/Right channel clock (LRCK) and Bit clock (BITCK) are not properly synchronized with the Master
clock (MCK) and R0 is set to ‘1’, a “Sync Reset” is generated. If R1 is also set to ‘1’ a hard mute is issued
during the Sync Reset and released after the Sync Reset is released.
During a Sync Reset the DATAnn inputs are ignored and digital silence is substituted. The TCD6001 waits
for the clocks to be synchronized before coming out of reset. During Sync Reset, the internal automatic DC
offset calibration values are cleared. When the clocks are restored, the system will need to be re-calibrated
by hard muting and un-muting or by forcing a DC calibration value in the Calibration Bank.
The Sync Reset is different from an external reset, which is created by pulling the RESETB pin low. A Sync
Reset will not change the values of I2C addressable read/write registers.
R1 enables a “Hard-mute” upon Sync Reset. When the Sync Reset condition is removed, an auto-calibration
will take place before the outputs are restored. R0 must be set to ‘1’ for R1 to have any effect.
The Master Clock (MCK) input frequency is determined by a combination of the S4X, S2X, and HFR bits and
the sampling frequency. The phase of MCK is not critical, as long as the frequency is correctly set. When the
HFR bit (register 23h, bit D3) is set to ‘1’, the TCD6001 divides MCK by 2 so that higher frequency system
clocks may be used. The duty cycle of MCK should be between 48% and 52% unless HFR is set to ‘1’. In
this case, the division automatically creates a 50% duty cycle internal clock.
MCK pulses
per sample
HFR
S4X
S2X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
128
64
64
512
256
128
128
The following table shows some examples of the MCK clock frequency based on sampling rate and HFR:
Data sampling rate
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
MCK frequency (HFR = ‘0’)
MCK frequency (HFR = ‘1’)
8.192 MHz
16.384 MHz
11.289 MHz
22.578 MHz
12.288 MHz
24.576 MHz
12.288 MHz
24.576 MHz
12.288 MHz
24.576 MHz
Digital Input Format
Addr
24h
Register Name
Digital Input Format
Default
D7
0
D6
DP
0
D5
D4
CCK
0
D3
I2S
0
D2
D1
DW1
1
D0
DW0
1
BCK
1
LRA
0
0
This register allows the user to specify the following digital interface characteristics:
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Input data width (DW0 and DW1)
Input data alignment with respect to LRCK clock edges (LRA)
Polarity of the LRCK clock (CCK)
Polarity of the BITCK clock (BCK)
Polarity of the input data (DP)
The TCD6001 receives PCM digital audio data in I2S format or variations thereof. The format consists of an
audio data input (DATAnn), a bit clock (BITCK) that runs at 64x the sampling frequency, and a 1x sampling
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TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
