TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.10.3 Register 64 – HVIO_CFG
Bit
Description
ECAT
PDI
Range [Unit]
7:0
HV_SLOPE_SLOW
-/w
-/w
With these option bits set to 1, the output slope
of the MFC_HV[i] pin can be slowed down.
15:8
HV_WEAK_HIGH
-/w
-/w
-/w
-/w
-/w
-/w
With these option bits set to 1, the high level
driver strength of the MFC_HV[i-8] pin can be
reduced.
23:16 HV_WEAK_LOW
With these option bits set to 1, the low level
driver strength of the MFC_HV[i-16] pin can be
reduced.
27:24 HV_DIFF_INPUT_EN
With these option bits set to 1, two of the
MFC_HV inputs can be combined to a differ-
ential input pair.
Bit 24 = 1 = MFC_HV3 & MFC_HV0
Bit 25 = 1 = MFC_HV4 & MFC_HV1
Bit 26 = 1 = MFC_HV5 & MFC_HV2
Bit 27 = 1 = MFC_HV7 & MFC_HV6
31:28 unused/reserved
-/-
-/-
Table 186: MFC IO Register 64 – HVIO_CFG
Note
This register can only be accessed from MFC CTRL SPI interface.
It cannot directly be accessed from ECAT master interface.
Nevertheless, the register content can be preloaded from SII EEPROM at startup.
Therefore, see Section 7.4.
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