TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
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6. Ramp Configurations for different Motion Profiles
Step generation is one of the main tasks of a stepper motor motion controller. The internal ramp
generator of TMC4330A provides several step generation configurations with different motion
profiles. They can be configured in combination with the velocity or positioning mode.
Pin Names: Ramp Generator
Pin Names
Type
Remarks
STPOUT_PWMA
DIROUT_PWMB
Output
Output
Step output signal.
Direction output signal.
Table 12: Pin Names: Ramp Generator
Register Names: Ramp Generator
Remarks
Register
Address
Register Name
GENERAL_CONF
0x00 RW Ramp generator affecting bits 5:0.
Additional step length in clock cycles; 16 bits.
STP_LENGTH_ADD
0x10 RW
Additional time in clock cycles when no steps will occur after a
direction change; 16 bits.
DIR_SETUP_TIME
RAMPMODE
XACTUAL
VACTUAL
AACTUAL
0x20 RW Requested motion profile and operation mode; 3 bits.
0x21 RW Current internal microstep position; signed; 32 bits.
0x22
0x23
R
R
Current step velocity; 24 bits; signed; no decimals.
Current step acceleration; 24 bits; signed; no decimals.
Maximum permitted or target velocity; signed; 32 bits= 24+8 (24
bits integer part, 8 bits decimal places).
VMAX
0x24 RW
VSTART
VSTOP
0x25 RW Velocity at ramp start; unsigned; 31 bits=23+8.
0x26 RW Velocity at ramp end; unsigned; 31 bits=23+8.
At this velocity value, the aceleration/deceleration will change during
0x27 RW
VBREAK
trapezoidal ramps; unsigned; 31 bits=23+8.
Maximum permitted or target acceleration; unsigned; 24 bits=22+2
(22 bits integer part, 2 bits decimal places).
AMAX
0x28 RW
DMAX
0x29 RW Maximum permitted or target deceleration; unsigned; 24 bits=22+2.
Acceleration at ramp start or below VBREAK; unsigned; 24
ASTART
0x2A RW
bits=22+2.
Deceleration at ramp end or below VBREAK; unsigned; 24
bits=22+2.
First bow value of a complete velocity ramp; unsigned; 24 bits=24+0
(24 bits integer part, no decimal places).
Second bow value of a complete velocity ramp; unsigned;
24bits=24+0.
Third bow value of a complete velocity ramp; unsigned; 24
bits=24+0.
DFINAL
BOW1
BOW2
BOW3
BOW4
0x2B RW
0x2D RW
0x2E RW
0x2F RW
Fourth bow value of a complete velocity ramp; unsigned; 24
0x30 RW
bits=24+0.
CLK_FREQ
XTARGET
0x31 RW External clock frequency fCLK; unsigned; 25 bits.
0x37 RW Target position; signed; 32 bits.
Table 13: Register Names: Ramp Generator
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