TMC211 DATASHEET (V. 1.04 / January 7, 2005)
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6.5 Physical Address of the circuit
The circuit must be provided with a physical address in order to discriminate this circuit from other
ones on the LIN bus. This address is coded on seven bits, yielding the theoretical possibility of 128
different circuits on the same bus. It is a combination of four OTP memory bits (see 5.2.3 OTP Memory
Structure) and three hardwired address bits (pins HW0, HW1 and HW2). Pins HW0 and HW1 are 5V
digital inputs, whereas pin HW2 is compliant with a 12V level. HW2 must either be connected to Vbat
or ground. Pin HW2 uses the same principle to check whether it is connected to ground or Vbat like
the SWI input (see 5.1.9 External Switch).
The TCM211 supports broadcasting. When the <Broad> bit is set to zero, broadcasting is active and
each slave on the LIN bus will be addressed.
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Physical address
OTP Memory
OTP_AD3 OTP_AD2 OTP_AD1 OTP_AD0
HW0
HW1
HW2
Hardwired Bits
Figure 16: Physical Slave Address
The amount of physical addresses can be expanded by using bit ADM. This bit allows for the following
expansion:
ADM
AD6
HW0
PA0
AD5
HW1
HW0
AD4
HW2
HW1
AD3
PA3
AD2
PA2
PA3
AD1
PA1
PA2
AD0
PA0
PA1
0
1
HW2
Table 13: Physical Address Expansion
6.6 Electro Magnetic Compability
EMC behavior fulfills requirements defined by LIN specification rev. 1.3.
6.7 Error Status Register
The LIN interface implements a register containing an error status of the LIN communication. This
register is specified as follows:
Bit7
Not used
Bit6
Not used
Bit5
Not used
Bit4
Not used
Bit3
Bit2
Bit1
Bit0
Timeout
Data Error
Header
Bit Error
Error Flag
Flag
Error Flag
Flag
Table 14: LIN Error Status Register
Note:
Data Error Flag = Checksum error OR StopBit error OR Length error
Header Error Flag = Parity error OR Synch Field error
A GetFullStatus command will reset the error status register
Copyright © 2004-2005 TRINAMIC Motion Control GmbH & Co. KG
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
