TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
17
4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
SDI
tDU
tDH
bit39
bit38
bit0
bit0
tDO
tZC
bit39
bit38
SDO
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
AC-Characteristics
clock period: tCLK
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SCK valid before or after change
of CSN
tCC
10
ns
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*)
CSN high time
tCSH
tCLK
>2tCLK+10
ns
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
*)
SCK low time
SCK high time
tCL
tCLK
>tCLK+10
>tCLK+10
ns
ns
*)
tCH
tCLK
assumes minimum
OSC frequency
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
fSCK
fSCK
tDU
4
8
MHz
MHz
ns
assumes
synchronous CLK
10
10
tDH
ns
no capacitive load
on SDO
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
tDO
tFILT
tFILT+5
30
ns
rising and falling
edge
12
20
ns
www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
