TSA7887
and performance will degrade. Figure 6 illustrates
how the TSA7887’s harmonic performance as a
function of frequency is affected by different source
impedances.
up the TSA7887 again. When the TSA7887 is
programmed in PM Mode 1 (i.e., [PM1,PM0] = [0,0],
the default condition), the TSA7887 is powered
down on a low-to-high CS transition and powers up
from shutdown on a high-to-low CS transition. If the
The TSA7887’s Internal 2.5-V Reference
CS pin is toggled low-to-high during the conversion
in this operating mode, the ADC is immediately
powered down.
Using the REF bit (the DB5 bit) in the TSA7887’s
Control Register, the TSA7887’s internal 2.5-V
reference can be enabled (DB5 cleared to “0”) or
disabled (DB5 set to “1”). If enabled (the default
condition), the internal voltage reference can be
used in applications for other purposes and, if this is
desired, the reference should be buffered by an
external, precision op amp. If an external, precision
voltage reference is to be used instead of the
TSA7887’s internal reference, the internal reference
is automatically overdriven. In this case, the
TSA7887’s internal reference should be disabled by
setting the REF bit in the control register. When the
internal reference is disabled, switch SW1 as shown
in Figure 7 opens and the input impedance seen at
the AIN1/VREF pin is the reference buffer’s input
Cold-Start and Standby Power-Up Delay Times
When VDD is first applied to the TSA7887 (in other
words, from cold start-up), the ADC powers up in PM
Mode 1 ([PM1,PM0] = [0,0]). Upon a subsequent
high-to-low CS transition, the TSA7887’s power-up
delay time is approximately 5μs When using an
external voltage reference in single-channel
operation or when the TSA7887 is powered up from
standby mode (PM Mode 4), its power-up delay time
is approximately 1μs because the internal reference
has been either disabled (refer to Control Register
DB5) or the internal reference has remained
powered up (via PM Mode 4). Since the TSA7887’s
power-up delay time PM Mode 4 is very short,
powering up the ADC and executing a conversion
with valid results in the same read/write operation is
feasible.
TSA7887 Power Consumption vs.
Throughput Rate Considerations
Figure 7: TSA7887’s Integrated 2.5-V VREF Circuitry.
In operating the TSA7887 in auto-shutdown mode
(PM Mode 3), in auto-standby mode (PM Mode 4),
or in PM Mode 1, the average power drawn by the
TSA7887 decreases at lower throughput rates. As
shown in Figure 8, the average power drawn from
impedance, approximately in the gigaohm range
(GΩ). When the internal reference is enabled, the
input impedance at the AIN1/VREF pin is typically
10kΩ. When the TSA7887 is configured for two-
channel operation, the TSA7887’s reference is set
internally to VDD.
Figure 8: TSA7887 Power Consumption
vs Throughput Rate
10
TSA7887’s Power-Down Operating Modes
VDD = 5V
SCLK = 2MHz
The TSA7887 provides flexible power management
to allow the user to achieve the best power
performance for a given throughput rate. The four
power management options are selected by
programming the TSA7887’s power management
bits (“PM” Bits PM1 and PM0) in the control register
as summarized in Table 6. When the PM bits are
programmed for either of the auto power-down
modes (PM Mode 3 or 4), the TSA7887 is powered-
down on the 16th low-to-high SCLK transition after a
1
VDD = 3V
SCLK = 2MHz
0.1
0.01
high-to-low CS transition. The first high-to-low SCLK
transition after a high-to-low CS transition powers-
0
20
30
40
10
50
THROUGHPUT RATE - ksps
TSA7887DS r1p0
Page 11
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
