TS7003
DESCRIPTION OF OPERATION
Converter Operation
Analog Input
The TS7003 uses an input track-and-hold (T/H) and a
successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 12-bit
output. No external-hold capacitor is needed for the
track/hold circuit. Figure 3 illustrates the TS7003 in its
simplest configuration. The TS7003 converts input
Figure 4 illustrates the sampling architecture of the
Figure 4: TS7003 Equivalent Input Circuit
Details.
analog-to-digital converter’s comparator. The full-
scale input voltage is set by the TS7003’s internal
2.5-V reference.
Figure 3: TS7003 Typical Application Circuit.
Track-and-Hold Operation
signals within the 0V to VREF range in 3.3μs including
the track-and-hold’s acquisition time. The serial
During track mode, the analog signal is acquired and
stored on the internal hold capacitor. During hold
mode, the track/hold switches SW1 and SW2 are
opened thereby maintaining a constant input level to
the converter’s SAR subcircuit.
interface requires only three digital lines (SCLK, CS,
and DOUT) and provides an easy interface to
microprocessors (μPs) and microcontrollers (μCs).
The TS7003 has two operating modes: normal and
During the acquisition phase with SW1 and SW2 on
TRACK, the input capacitor, CHOLD, is charged to the
shutdown. Toggling (or driving) the SHꢀꢁ pin low
shuts down the ADCs and reduces supply current
below 1 μA when VDD ≤ 3.6V. Open-circuiting or
analog input (AIN). Toggling the CS pin low causes
the acquisition process to stop. At this instant,
track/hold switches SW1 and SW2 are moved to
HOLD position and the input side of CHOLD is then
switched to GND. Unbalancing Node ZERO at the
comparator’s input, the retained charge on CHOLD
represents a sample of the input signal applied to the
converter.
toggling (or driving) the SHꢀꢁ pin high or places the
ADCs into operational mode. Toggling the CS pin to
logic low initiates a conversion where the conversion
result is available at DOUT in unipolar serial format.
The serial data stream consists of three leading zeros
followed by the data bits with the MSB first. All
transitions on the DOUT pin occur within 20ns after
the low-to-high transition of SCLK. Serial interface
timing details of the TS7003 are illustrated in Figures
8 and 9.
In hold mode and to restore Node ZERO to 0V within
the limits of the converter’s 12- bit resolution, the
output of the capacitive digital-to-analog converter
(the CDAC) is adjusted during the remainder of the
conversion cycle. In other words, the stored charge
on CHOLD is transferred to the binary-weighted CDAC
where it is converted into a digital representation of
the analog input signal. At end of the conversion
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TS7003DS r1p0
RTFDS
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