TS7003
Usingꢄ theꢄ Aꢂ ’sꢄ ꢀꢁꢂꢃ to Reduce Operating
Supply Current
A CS high-to-low transition initiates the conversion
sequence - the input track-and-hold samples the input
signal level, the ADC begins to convert, and the
DOUT pin changes state from high impedance to
logic low. The external SCLK signal is used to drive
the conversion process and is also used to transfer
the converted data out of the ADC as each bit of
conversion is determined.
Power consumption can be reduced significantly by
turning off the TS7003 in between conversions.
Figure 5: TS7003 Supply Current vs Conversion Rate
1k
VDD = 3V
DOUT = FS
RL = ∞
CL = 10pF
The SCLK signal transfers data after a low-to-high
transition of the third (3rd) SCLK pulse. After each
subsequent SCLK rising edge, transitions on the
DOUT pin occur in 20ns. The third rising clock edge
produces the MSB of the conversion at DOUT,
followed by the remaining bits. Since there are twelve
data bits and three leading zeros, at least fifteen
rising clock edges are needed to transfer the entire
data stream. Extra SCLK pulses occurring after the
conversion result has been completely transferred out
100
10
1
and, before to a new, low-to-high transition on CS,
produce a string trailing zeros at DOUT. In addition,
the extra SCLK pulses have no effect on converter
operation.
0.1
0.1
1
10
100
1k
CONVERSION RATE - ksps
Figure 5 illustrates the TS7003’s average supply
current versus conversion rate. The wake-up delay
Minimum conversion cycle time can be accomplished
by: (a) toggling the CS pin high after reading the
conversion result’s LSB; and (b), after the specified
minimum time defined by tCS has elapsed, toggling
time (tWAKE) is the time from when the SHꢀꢁ pin is
deasserted to the time when a conversion may be
initiated (Refer to Figure 6). This delay time depends
on how long the ADC was in shutdown (Refer to
Figure 7) because the external 4.7μF reference
bypass capacitor is discharged slowly when
the CS pin low again to initiate the next conversion.
Output Data Coding and Transfer Function
SHꢀꢁ = 0.
Conversion results at the TS7003’s ꢀOUT pin are
straight binary data. Figure 10 illustrates the nominal
transfer function where code transitions occur halfway
between successive integer LSB values. If
VREF = +2.500V, then 1 LSB = 610μV or 2.500V/4096.
Timing and Control Details
The CS and SCLK digital inputs control the TS7003’s
conversion-start and data-read operations. The
AꢀC’s serial-interface operations are illustrated in
Figures 8 and 9.
Figure 6: TS7003 Shutdown Operation.
Page 10
TS7003DS r1p0
RTFDS
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