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UCD90320ZWSR 参数 Datasheet PDF下载

UCD90320ZWSR图片预览
型号: UCD90320ZWSR
PDF下载: 下载PDF文件 查看货源
内容描述: [32 轨 PMBus 电源序列发生器和系统管理器 | ZWS | 169 | -40 to 85]
分类和应用:
文件页数/大小: 54 页 / 1588 K
品牌: TI [ TEXAS INSTRUMENTS ]
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UCD90320  
www.ti.com.cn  
ZHCSFI3B AUGUST 2016REVISED MAY 2019  
A re-sequencing event can be repeated for one to approximately four times or unlimited times. The Time  
Between Re-Sequences period begins to increment when all the relevant rails are given Not Power Good  
statuses. When the time period elapses, a re-sequence event begins. When the Enable Re-Sequence Abort is  
checked, the re-sequence event aborts if any relevant rail triggers a Max Turn Off warning. However, the Max  
Turn Off warning does not stop an ongoing re-sequence event. If any rails at the re-sequence state are caused  
by a GPI fault response, the device suspends the entire re-sequence event until the GPI fault is physically clear.  
It is also configurable to ignore the POWER_GOOD_OFF and TOFF_MAX_WARN status of a rail when  
performing re-sequencing if the corresponding bits are set.  
After the Rail Sequence is configured, the GUI displays simulated sequence timing in the Vout Config tab. It  
demonstrates the dependencies among the rails. An example is shown in Figure 15. The rails power-on and  
power-off slew rates in Figure 15 are for demonstration purpose only.  
Figure 15. Simulated Sequence Timing Window (Rail Config)  
Copyright © 2016–2019, Texas Instruments Incorporated  
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