SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
UCC1895
UCC2895
UCC3895
ABSOLUTE MAXIMUM RATINGS
−40°C
≤
TA
≤
85°C, all voltage values are with respect to the network ground terminal unless otherwise noted. (2)
UCC2895N
Supply voltage
Supply current
Reference current
Output crrent
Analog inputs
Drive outputs
Power dissipation at TA = 25°C
Storage temperature range, Tstg
Junction temperature range, TJ
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB
OUTA, OUTB, OUTC, OUTD
DW−20 package
N−20 package
(IDD < 10 mA)
17
30
15
100
−0.3 V to REF+0.3 V
−0.3 V to VCC + 0.3 V
650
1
−65 to 150
−55 to 150
°C
C
V
mW
W
mA
UNIT
V
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS
(3)
MIN
Supply voltage, VDD
Supply voltage bypass capacitor, VDD(1)
Reference bypass capacitor, CREF(2)
Timing capacitor, CT (for 500 kHz switching frequency)
Timing resistor, RT (for 500 kHz switching frequency)
Delay resistor RDEL_AB, RDEL_CD
2.5
9
10 x CREF
0.1
220
82
40
1.0
TYP
MAX
16.5
UNIT
V
µF
F
pF
kΩ
Operating junction temperature, TJ(4)
−55
125
°C
(1) The VDD capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor should
belocated as physically close as possible to the VDD pins.
(2) The VREF capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired
for the VREF then it should be located near the VREF cap and connected to the VREF pin with a resistor of 51
Ω
or greater. The bulk capacitor on
VDD must be a factor of 10 greater than the total VREF capacitance.
(3) It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a seperate ground
plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located over this ground plane. Any
connections associated with these pins to ground should be connected to this ground plane.
(4) It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
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