SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
UCC1895
UCC2895
UCC3895
BLOCK DIAGRAM
IRT
RT
8
8(IRT )
CT
7
Q
OSC
Q
R
Q
SYNC
6
PWM
COMPARATOR
RAMP
3
+
0.8 V
EAOUT
2
ERROR
AMP
+
CURRENT SENSE
COMPARATOR
+
D S
Q
NO LOAD
COMPARATOR
+
0.5 V / 0.6 V
16
PGND
+
OUTC
D S
Q
DELAY A
D S
Q
15
VDD
18
9
OUTA
DELAB
R
Q
DELAY B
17
OUTB
DELAY C
14
10
EAP
20
DELCD
OUTD
EAN
R
Q
1
2V
DELAY D
13
CS
12
OVER CURRENT
COMPARATOR
ADAPTIVE DELAY
SET AMPLIFIER
+
Q
REF
IRT
HI = ON
0.5 V
Q
S
R
DISABLE
COMPARATOR
+
HI = ON
10(IRT)
+
UVLO COMPARATOR
+
11 V / 9 V
REF
REFERENCE OK
COMPARATOR
4V
0.5V
11
ADS
2.5 V
+
4
REF
SS
19
5
GND
UDG−98140
REF
VREF
8 x IRT
RT
RT
IRT
CT
2.5 V
+
CT
SYNC
0.2 V
+
R
CLOCK
UDG−03135
CLOCK
S
Q
Figure 1. Oscillator Block Diagram
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7