UCC2817A, UCC2818A
UCC3817A, UCC3818A
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009
Pin Descriptions (cont.)
IAC:
This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier
is tailored for very low distortion from this current input (I
IAC
) to multiplier output. The recommended maximum
I
IAC
is 500
µA.
MOUT:
The output of the analog multiplier and the inverting input of the current amplifier are connected together
at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured
as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge
modulation operation. The multiplier output current is limited to 2 I
IAC
. The multiplier output current is given
by the equation:
I
MOUT
+
I
IAC
(V
VAOUT
*
1)
V
VFF
2
K
where K
+
1 is the multiplier gain constant.
V
OVP/EN:
A window comparator input that disables the output driver if the boost output voltage is a programmed
level above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).
PKLMT:
The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense
resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the
peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
RT:
A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and
100 kΩ is recommended. Nominal voltage on this pin is 3 V.
SS:
V
SS
is discharged for V
VCC
low conditions. When enabled, SS charges an external capacitor with a current
source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase
slowly. In the event of a V
VCC
dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable
the PWM.
Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the
application section for details.
VAOUT:
This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output
is internally limited to approximately 5.5 V to prevent overshoot.
VCC:
Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC
directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To
prevent inadequate gate drive signals, the output devices are inhibited unless V
VCC
exceeds the upper
under-voltage lockout voltage threshold and remains above the lower threshold.
VFF:
The RMS voltage signal generated at this pin by mirroring 1/2 of the I
IAC
into a single pole external filter.
At low line, the VFF voltage should be 1.4 V.
VSENSE:
This is normally connected to a compensation network and to the boost converter output through a
divider network.
VREF:
VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA
to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when
V
VCC
is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best
stability. Please refer to Figures 8 and 9 for VREF line and load regulation characteristics.
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