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UC3825AN 参数 Datasheet PDF下载

UC3825AN图片预览
型号: UC3825AN
PDF下载: 下载PDF文件 查看货源
内容描述: 高速PWM控制器 [High Speed PWM Controller]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管信息通信管理PC
文件页数/大小: 15 页 / 302 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004  
LEADING EDGE BLANKING  
The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The  
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less  
than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.  
Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.  
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.  
On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM  
comparator, current limit comparator, or the overcurrent comparator.  
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.  
Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the  
pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not  
require any filtering as result of leading edge blanking.  
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and  
the internal 10-kresistor determines the blanked interval. The 10-kresistor has a 10% tolerance. For more accuracy,  
an external 2-k1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kwith a tolerance of 2.4%.  
The design equation is:  
ǒ Ǔ  
+ 0.5   R ø 10 kW   C  
t
LEB  
(2)  
Values of R less than 2 kshould not be used.  
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,  
the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults  
without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this  
reason, some noise filtering may be required on the ILIM pin.  
UDG−95105  
Figure 4. Leading Edge Blanking Operational Waveforms  
7