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SCES640C – JANUARY 2007 – REVISED MAY 2009
PRINCIPLES OF OPERATION
Applications
The TXS0102 can be used to bridge the digital-switching compatibility gap between two voltage nodes to
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point
topology for interfacing devices or systems operating at different interface voltages with one another. Its primary
target application use is for interfacing with open-drain drivers on the data I/Os such as I
2
C or 1-wire, where the
data is bidirectional and no control signal is available. The TXS0102 can also be used in applications where a
push-pull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull
applications.
Architecture
The TXS0102 architecture (see
is an auto-direction-sensing based translator that does not require a
direction-control signal to control the direction of data flow from A to B or from B to A.
V
CCA
V
CCB
T1
R1
10k
One
One-
shot
shot
One
One-
shot
shot
T2
R2
10k
Gate Bias
A
N2
B
Figure 1. Architecture of a TXS01xx Cell
These two bidirectional channels independently determine the direction of data flow without a direction-control
signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this
auto-direction feature is realized.
The TXS0102 is part of TI's "Switch" type voltage translator family and employs two key circuits to enable this
voltage translation:
1) An N-channel pass-gate transistor topology that ties the A-port to the B-port
and
2) Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability.
The V
GATE
gate bias of the N-channel pass transistor is set at approximately one threshold voltage (V
T
) above
the V
CC
level of the low-voltage side. Data can flow in either direction without guidance from a control signal.
The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for
transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S.
circuits turn on the PMOS transistors (T1, T2) to increase the current drive capability of the driver for
approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high
ac drive by bypassing the internal 10-kΩ pull-up resistors during the low-to-high transition to speed up the signal.
The output resistance of the driver is decreased to approximately 50
Ω
to 70
Ω
during this acceleration phase. To
minimize dynamic I
CC
and the possibility of signal contention, the user should wait for the O.S. circuit to turn-off
before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width
number provided in the
Timing Requirements
section of this data sheet.
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