TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 3-50. Status 2
Subaddress 3Bh
Read only
7
6
5
4
3
2
1
0
Signal present
Weak signal
detection
PAL switch
polarity
Field sequence
status
Color killed
Macrovision detection [2:0]
Signal present detection:
0 = Signal not present
1 = Signal present
Weak signal detection:
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field:
0 = PAL switch is 0b
1 = PAL switch is 1b
Field sequence status:
0 = Even field
1 = Odd field
Color killed:
0 = Color killer not active
1 = Color killer activated
Macrovision detection [2:0]:
000 = No copy protection
001 = AGC pulses/pseudo syncs present (Type 1)
010 = 2-line colorstripe only present
011 = AGC pulses/pseudo syncs and 2-line colorstripe present (Type 2)
100 = Reserved
101 = Reserved
110 = 4-line colorstripe only present
111 = AGC pulses/pseudo syncs and 4-line colorstripe present (Type 3)
Table 3-51. AGC Gain Status
Subaddress 3Ch–3Dh
Read only
Subaddress
3Ch
7
6
5
4
3
2
1
0
Fine Gain [7:0]
3Dh
Coarse Gain [3:0]
Fine Gain[11:8]
Fine gain [11:0]: This register provides the fine gain value of sync channel.
1111 1111 1111 = 1.9995
1000 0000 0000 = 1
0100 0000 0000 = 0.5
Coarse gain [3:0]: This register provides the coarse gain value of sync channel.
1111 = 2
0101 = 1
0000 = 0.5
These AGC gain status registers are updated automatically by the TVP5160 decoder with AGC on, in manual gain control mode these
register values are not updated by the TVP5160 decoder.
Because this register is a multi-byte register, it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of I2C register 97h (status request)
must be set to 1b. Once the internal processor has updated this register, bit 0 of register 97h is cleared, indicating that both bytes of the
AGC gain status register have been updated and can be read. Either byte may be read first, because no further update occurs until bit 0 of
97h is set to 1b again.
62
Internal Control Registers
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