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TVP5150AM1PBSR 参数 Datasheet PDF下载

TVP5150AM1PBSR图片预览
型号: TVP5150AM1PBSR
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗NTSC , PAL , SECAM视频解码器 [Ultralow-Power NTSC,PAL,SECAM Video Decoder]
分类和应用: 解码器转换器色度信号转换器消费电路商用集成电路电视PC
文件页数/大小: 88 页 / 1177 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SLES209E
NOVEMBER 2007
REVISED OCTOBER 2011
6 Application Information
6.1
Application Example
C2
1 µF
IO_DVDD
C1
1 µF
C3
1 µF
10 k
W
See Note I
PDN
INTREQ/GPCL/VBLK
AVID
HSYNC
PDN
INTREQ/GPCL/VBLK
AVID
HSYNC
R1
CH1_IN AAF
37.4
W
C4
0.1 µF
0.1 µF
AVDD
10 kW
See Note H
32
31
30
29
28
27
26
25
IO_DVDD
CH_AVDD
CH_AGND
REFM
REFP
PDN
INTREQ/GPCL/VBLK
AVID
HSYNC
R2
37.4
W
C11
R3
2.2 kW
R4
2.2 kW
R5
CH2_IN AAF
37.4
W
R6
37.4
W
C5
0.1 µF
AVDD
C6
0.1 µF
OSC_IN
Y1
14.31818 MHz ± 50 ppm
IO_DVDD
C8
CL1
R
CL2
C9
C10
0.1 µF
IO_DVDD
SCLK
SCLK
RESETB
9
10
11
12
13
14
15
16
OSC_IN
1
S1
2
SCLK
IO_DVDD
YOUT7/I2CSEL
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
1
2
3
4
5
6
7
8
AIP1A
AIP1B
PLL_AGND
PLL_AVDD
TVP5150AM1
XTAL1/OSC_IN
XTAL2
AGND
RESETB
VSYNC/PALI
FID/GLCO
SDA
SCL
DVDD
DGND
YOUT0
YOUT1
24
23
22
21
20
19
18
17
VSYNC/PALI
FID/GLCO
SDA
SCL
VSYNC/PALI
FID/GLCO
DVDD
C7
0.1 µF
YOUT[7:0]
R7
10 kW
Implies I C address is BAh. If B8h is to be used,
connect pulldown resistor to digital ground.
2
A.
B.
C.
D.
E.
F.
G.
H.
I.
The use of INTREQ/GPCL/VBLK, AVID, HSYNC, and VSYNC/PALI is optional.
When OSC_IN is connected through S1, remove the capacitors for the crystal.
PDN needs to be high, if device has to be always operational.
RESETB is operational only when PDN is high. This allows an active-low reset to the device.
100-kΩ resistor (R) in parallel with the crystal is recommended for most crystal types.
Anti-aliasing filter (AAF) highly recommended for best video quality.
System level ESD protection is not included in this application circuit, but it is highly recommended on the analog
video inputs.
An external 10-kΩ pulldown resistor is required when the INTREQ/GPCL/VBLK output (pin 27) is disabled (bit 5 of I
2
C
register 03h is set to 0).
An external 10-kΩ pullup resistor is required when the INTREQ/GPCL/VBLK output (pin 27) is enabled and
configured as an active-low interrupt (bit 5 of I
2
C register 03h is set to 1, bit 1 of I
2
C register 0Fh is set to 0, and bit 0
of I
2
C register 1Eh is set to 0).
Figure 6-1. Application Example
80
Application Information
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2007–2011, Texas Instruments Incorporated