HS
First Field
VS
B/2
B/2
HS
Second Field
VS
H/2 + B/2
H/2 + B/2
10-Bit (PCLK = 2
Mode
NTSC 601
PAL 601
NTSC Sqp
PAL Sqp
B/2
64
64
64
64
Pixel Clock)
H/2
858
864
780
944
20-Bit (PCLK = 1
B/2
32
32
32
32
Pixel Clock)
H/2
429
432
390
472
Figure 2−25. VSYNC Position Respect to HSYNC
2.5.3
Embedded Syncs
Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges
of AVID. These codes contain the V and F bits which also define vertical timing. Table 2−4 gives the format of the SAV
and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field
counter varies depending on the standard.
The P bits are protection bits:
P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H
Table 2−4. EAV and SAV Sequence
D9 (MSB)
Preamble
Preamble
Preamble
Status word
1
0
0
1
D8
1
0
0
F
D7
1
0
0
V
D6
1
0
0
H
D5
1
0
0
P3
D4
1
0
0
P2
D3
1
0
0
P1
D2
1
0
0
P0
D1
1
0
0
0
D0
1
0
0
0
2.6 I
2
C Host Interface
Communication with the TVP5146 decoder is via an I
2
C host interface. The I
2
C standard consists of two signals, the
serial input/output data (SDA) line and the serial input clock line (SCL), which carry information between the devices
connected to the bus. A third signal (I
2
CA) is used for slave address selection. Although an I
2
C system can be
multimastered, the TVP5146 decoder functions as a slave device only.
2−17
TI [ TEXAS INSTRUMENTS ]
