TPS767D3xx
SLVS209H–JULY 1999–REVISED AUGUST 2008......................................................................................................................................................... www.ti.com
TPS767D3xx
5
6
28
VIN
IN
IN
RESET
250kW
VOUT
RESET
24
23
OUT
OUT
C1
0.1mF
50V
4
EN
C
+
OUT
10mF
GND
3
Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel
TIMING DIAGRAM
VIN
(1)
VRES
VRES
t
(2)
VIT+
(2)
VOUT
VIT+
Threshold
Voltage
Less than 5% of
the output voltage
VIN
-
VIN
-
t
RESET
Output
200ms
Delay
200ms
Delay
Output
Undefined
Output
Undefined
t
(1) VRES is the minimum input voltage for a valid RESET.
(2) VIT —Trip voltage is typically 5% lower than the output voltage (95% VOUT).
6
Submit Documentation Feedback
Copyright © 1999–2008, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
