TPS717xx
SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009..................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT
TPS717xxyyyz
V
OUT (2)
XX
is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY
is package designator.
Z
is package quantity.
(1)
(2)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at
Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating temperature range (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
Input voltage range, V
IN
Feedback input voltage range, V
FB
, V
NR
Enable voltage range, V
EN
Output voltage range, V
OUT
Maximum output current, I
OUT
Continuous total power dissipation, P
DISS
Junction temperature range, T
J
Storage junction temperature range, T
STG
ESD rating, HBM
ESD rating, CDM
(1)
(2)
TPS717xx
–0.3 to +7.0
–0.3 to +3.6
–0.3 to V
IN
+ 0.3V
–0.3 to +7.0
Internally limited
See
Table
–55 to +150
–55 to +150
2
500
°C
°C
kV
V
(2)
UNIT
V
V
V
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
V
EN
absolute maximum rating is V
IN
+ 0.3V or +7.0V, whichever is greater.
DISSIPATION RATINGS
BOARD
Low-K
(1)
High-K
High-K
High-K
(1)
(2)
(2)
PACKAGE
DCK
DCK
DRV
DRV
DSE
R
θJC
165°C/W
165°C/W
20°C/W
20°C/W
—
R
θJA
395°C/W
315°C/W
140°C/W
65°C/W
206°C/W
DERATING FACTOR
ABOVE T
A
= +25°C
2.5mW/°C
3.2mW/°C
7.1mW/°C
15.4mW/°C
4.85mW/°C
T
A
< +25°C
250mW
320mW
715mW
1540mW
485mW
T
A
= +70°C
140mW
175mW
395mW
845mW
269mW
T
A
= +85°C
100mW
130mW
285mW
615mW
194mW
Low-K
(1)
(2)
(2)
The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2
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