TPS61010, TPS61011
TPS61012, TPS61013
TPS61014, TPS61015, TPS61016
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SLVS314C–SEPTEMBER 2000–REVISED OCTOBER 2003
APPLICATION INFORMATION (continued)
Figure 34. TPS6101x EVM Bottom Layer Layout (actual size: 55,9 mm x 40,6 mm)
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are:
•
•
•
Improving the power dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
The maximum junction temperature (TJ) of the TPS6101x devices is 125°C. The thermal resistance of the 10-pin
MSOP package (DGS) is RΘJA = 294°C/W. Specified regulator operation is assured to a maximum ambient
temperature (TA) of 85°C. Therefore, the maximum power dissipation is about 130 mW. More power can be
dissipated if the maximum ambient temperature of the application is lower.
T
– T
J(MAX)
R
A
125° C * 85° C
294° CńW
P
+
+
+ 136 mW
D(MAX)
QJA
(8)
23
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