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TPS61015DGS 参数 Datasheet PDF下载

TPS61015DGS图片预览
型号: TPS61015DGS
PDF下载: 下载PDF文件 查看货源
内容描述: 高效率, 1节和2节电池升压转换器 [HIGH-EFFICIENCY, 1-CELL AND 2-CELL BOOST CONVERTERS]
分类和应用: 转换器稳压器开关式稳压器或控制器电源电路电池开关式控制器光电二极管功效升压转换器
文件页数/大小: 25 页 / 452 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS61010, TPS61011  
TPS61012, TPS61013  
TPS61014, TPS61015, TPS61016  
www.ti.com  
SLVS314CSEPTEMBER 2000REVISED OCTOBER 2003  
DESIGN PROCEDURE (continued)  
Capacitor CC1 depends on the ESR and capacitance value of the output capacitor, and on the value chosen for  
RC. Its value is calculated using Equation 7.  
C
ESR  
OUT  
COUT  
C
+
C1  
R
C
(7)  
For a selected output capacitor of 22 µF with an ESR of 0.2, an RC of 33 k, the value of CC1 is in the range  
of 100 pF.  
Table 2. Recommended Compensation Components  
OUTPUT CAPACITOR  
INDUCTOR[µH]  
RC[k]  
CC1[pF]  
CC2[nF]  
CAPACITANCE[µF]  
ESR[]  
0.2  
33  
22  
10  
10  
22  
22  
22  
10  
33  
120  
150  
100  
10  
33  
22  
10  
10  
0.3  
47  
0.4  
100  
100  
0.1  
LAYOUT CONSIDERATIONS  
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents  
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as  
well as EMI problems.  
Therefore, use wide and short traces for the main current path as indicated in bold in Figure 25. The input  
capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common  
ground node as shown in Figure 25 to minimize the effects of ground noise. The compensation circuit and the  
feedback divider should be placed as close as possible to the IC. To layout the control ground, it is  
recommended to use short traces as well, separated from the power ground traces. Connect both grounds close  
to the ground pin of the IC as indicated in the layout diagram in Figure 25. This avoids ground shift problems,  
which can occur due to superimposition of power ground current and control ground current.  
U1  
L1  
SW  
VOUT  
LBO  
R4  
LBO  
Battery  
C4  
C1  
OUTPUT  
VBAT  
R2  
R3  
R5  
R6  
LBI  
FB  
R1  
C2  
ADEN  
COMP  
C3  
EN  
GND  
Figure 25. Layout Diagram  
18  
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