TPS54260
www.ti.com
SLVSA86 –MARCH 2010
DEVICE INFORMATION
PIN CONFIGURATION
MSOP10
(TOP VIEW)
BOOT
VIN
10
9
1
2
3
4
PH
GND
COMP
Thermal
Pad
(11)
8
EN
SS/TR
7
VSENSE
PWRGD
RT/CLK
6
5
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
BOOT
1
O
O
I
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
COMP
EN
8
3
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
GND
PH
9
–
I
Ground
10
11
The source of the internal high-side power MOSFET.
POWERPAD
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.
PWRGD
6
5
4
O
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.
RT/CLK
SS/TR
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
I
VIN
2
7
I
I
Input supply voltage, 3.5 V to 60 V.
VSENSE
Inverting node of the transconductance ( gm) error amplifier.
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