TPS54383, TPS54386
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SLUS774B–AUGUST 2007–REVISED OCTOBER 2007
V BR R min ³ 1.2´ V
IN
( ) (
)
(27)
The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used.
The average current in the rectifier diode is estimated by Equation 28.
I
» I
´ 1- D
( )
OUT max
D avg
(
)
(
)
(28)
For this design, 1.2-A (average) and 2.25 A (peak) is estimated for Channel 1 and 1.5-A (average) and 2.21-A
(peak) for Channel 2.
An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward
voltage drop of 0.4 V at 2 A.
The power dissipation in the diode is estimated by Equation 29.
PD max » VFM ´ ID avg
)
(
)
(
(29)
For this design, the full load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2.
Output Capacitor Selection
The TPS54383's internal compensation limits the selection of the output capacitors. From Figure 25, the internal
compensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30.
1
COUT
=
2
)
4´ p2 ´ f
´L
(
RES
(30)
Solving for COUT using
•
•
fRES = 3 kHz
L = 22 µH
The resulting is COUT = 128 µF. The output ripple voltage of the converter is composed of the ripple voltage
across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the
maximum ESR allowable to meet the output ripple requirements the total ripple is partitioned, and the equation
manipulated to find the ESR.
VRIPPLE(tot) - VRIPPLE(cap) VRIPPLE(tot)
=
D
ESR(max)
=
-
IRIPPLE
IRIPPLE
fS ´ COUT
(31)
Based on 128 µF of capacitance, 300-kHz switching frequency and 50-mV ripple voltage plus rounding up the
ripple current to 0.5 A, and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a
maximum allowable ESR of 87 mΩ.
To meet the ripple voltage requirements, a low-cost 100-µF electrolytic capacitor with 400 mΩ ESR (C5, C17)
and two 10-µF ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-mΩ ESR are selected. From the
datasheets for the ceramic capacitors, the parallel combination provides an impedance of 28 mΩ @ 300 kHz for
14 mV of ripple.
Voltage Setting
The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 kΩ and 50 kΩ to
maintain a balance between power dissipation and noise sensitivity. For this design, 20 kΩ is selected.
The lower resistors, R4 and R7 are found using the following equations.
Copyright © 2007, Texas Instruments Incorporated
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