TPS54383, TPS54386
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SLUS774B–AUGUST 2007–REVISED OCTOBER 2007
to support the desired regulation voltage by the time Soft Start has completed, then
the output UV circuit may trip and cause a hiccup in the output voltage. In this case,
use a timed delay startup from the ENx pin to delay the startup of the output until the
PVDDx voltage has the capability of supporting the desired regulation voltage. See
Operating Near Maximum Duty Cycle and Maximum Output Capacitance for related
information.
Output Voltage Regulation
Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse
width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider
connecting the output node, the FBx pin, and GND (see Figure 21). Assuming the value of the upper voltage
setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by
Equation 2.
VREF
R2 = R1´
VOUT - VREF
(2)
where
•
VREF is the internal 0.8-V reference voltage
TPS5438x
1
2
3
4
5
6
7
PVDD1 PVDD2 14
BOOT1 BOOT2 13
OUTPUT1
SW1
GND
EN1
EN2
FB1
SW2 12
BP 11
R1
SEQ 10
ILIM2
FB2
9
8
R2
UDG-07011
Figure 21. Feedback Network for Channel 1
DESIGN HINT
There is a leakage current of up to 12 µA out of the SW pin when a single output of
the TPS5438x is disabled. Keeping the series impedance of R1 + R2 less than 50 kΩ
prevents the output from floating above the referece voltage while the controller output
is in the OFF state.
16
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