SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007
www.ti.com
The TPS54311, TPS54312, TPS54313, TPS54314, TPS54315 and TPS54316 devices are available in a
thermally enhanced 20-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet aggressive equipment development cycles.
ORDERING INFORMATION
(1)
T
J
OUTPUT VOLTAGE
0.9 V
1.2 V
–55°C to 125°C
1.5 V
1.8 V
2.5 V
3.3 V
(1)
(2)
PACKAGED DEVICES PLASTIC HTSSOP
(PWP)
(2)
TPS54311MPWPREP
TPS54312MPWPREP
TPS54313MPWPREP
TPS54314MPWPREP
TPS54315MPWPREP
TPS54316MPWPREP
TOP SIDE MARKING
TPS54311
TPS54312
TPS54313
TPS54314
TPS54315
TPS54316
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
The PWP package is taped and reeled as indicated by the R suffix. See application section of data sheet for PowerPAD drawing and
layout information
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL FUNCTIONS
TERMINAL
NAME
AGND
BOOT
FSEL
NC
PGND
PH
PWRGD
RT
SS/ENA
VBIAS
VIN
VSENSE
NO.
1
5
19
3
11–13
6–10
4
20
18
17
14–16
2
DESCRIPTION
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT
resistor and FSEL pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for
the high-side FET driver.
Frequency select input. Provides logic input to select between two internally set switching frequencies.
No connection
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. Hi-Z when VSENSE
≥
90% V
ref
, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
a high quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input. Connect directly to output voltage sense point.
2
TI [ TEXAS INSTRUMENTS ]
