TPS54310
SLVS412A – DECEMBER 2001 – REVISED JUNE 2002
www.ti.com
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54310 application. The TPS54310 (U1) can provide
up to 3 A of output current at a nominal output voltage of
J1
VI
GND
VIN
2
1
C2
1
R1
10 kΩ
+
R3
71.5 kΩ
20
19
18
17
C3
0.1
µF
PWRGD
U1
TPS54310PWP
RT
SYNC
SS/ENA
VIN
VIN
VIN
PH
PH
16
15
14
10
9
+
C9
180
µF
4V
C7
0.047
µF
C11
1000 pF
L1
1.2
µH
1
2
J3
VO
GND
C8
10
µF
3.3 V. For proper thermal performance, the power pad
underneath the TPS54310 integrated circuit needs to be
soldered well to the printed circuit board.
VBIAS
4
PWRGD
3 COMP
C5
3900 pF
C4
100 pF
R2
3.74 kΩ
8
PH
7
PH
6
PH
2
VSENSE
5
BOOT
13
PGND
1
AGND
12
PGND
11
PGND
PwrPAD
C6
R4
3.74 kΩ
1
Optional
2700 pF
R5
R6
732
Ω
R7
49.9
Ω
10 kΩ
Figure 10. TPS54310 Schematic
INPUT VOLTAGE
The input to the circuit is a nominal 5 VDC, applied at J1.
The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A.
C8 is the decoupling capacitor for the TPS54310 and must
be located as close to the device as possible.
OUTPUT FILTER
The output filter is composed of a 1.2-µH inductor and
180-µF capacitor. The inductor is a low dc resistance
(0.017
Ω)
type, Coilcraft DO1813P-122HC. The capacitor
used is a 4-V special polymer type with a maximum ESR
of 0.015
Ω.
The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
FEEDBACK CIRCUIT
The resistor divider network of R5 and R4 sets the output
voltage for the circuit at 3.3 V. R5, along with R2, R6, C4,
C5, and C6 forms the loop compensation network for the
circuit. For this design, a Type 3 topology is used.
GROUNDING AND PowerPAD LAYOUT
The TPS54310 has two internal grounds (analog and
power). Inside the TPS54310, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54310,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground planes are
recommended. These two planes should tie together
directly at the IC to reduce noise between the two grounds.
The only components that should tie directly to the power
ground plane are the input capacitor, the output capacitor,
the input voltage decoupling capacitor, and the PGND pins
of the TPS54310. The layout of the TPS54310 evaluation
module is representative of a recommended layout for a
OPERATING FREQUENCY
In the application circuit, the 350-kHz operation is selected
by leaving RT and SYNC open. Connecting a 68-kΩ to
180-kΩ resistor between RT (pin 20) and analog ground
can be used to set the switching frequency from 280 kHz
to 700 kHz. To calculate the RT resistor, use the
equation 1:
R
+
100 kW
ƒ
SW
8
500 kHz
(1)
TI [ TEXAS INSTRUMENTS ]
