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TPS51200DRCRG4 参数 Datasheet PDF下载

TPS51200DRCRG4图片预览
型号: TPS51200DRCRG4
PDF下载: 下载PDF文件 查看货源
内容描述: 漏/源DDR终端稳压器 [SINK/SOURCE DDR TERMINATION REGULATOR]
分类和应用: 稳压器双倍数据速率
文件页数/大小: 35 页 / 1260 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS51200  
www.ti.com  
SLUS812FEBRUARY 2008  
Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the  
tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR  
JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).  
VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions  
The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.  
The TPS51200 ensures the regulator output voltage to be:  
VTTREF –25 mV < VTT < VTTREF + 25mV, for both DC and AC conditions and –2 A < IVTT < 2 A  
The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to  
DDR, DDR2, DDR3 and Low Power DDR3/DDR4 applications (see Table 1 for detailed information). To meet the  
stability requirement, a minimum output capacitance of 20 µF is needed. Considering the actual tolerance on the  
MLCC capacitors, three 10-µF ceramic capacitors are sufficient to meet the above requirement.  
Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology and Their Differences  
Low Power  
DDR  
DDR2  
DR3  
DDR3  
FSB Data Rates  
Termination  
200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz  
800, 1066, 1330 and 1600 MHz  
Same as DDR3  
On-die termination for data group. On-die termination for data group.  
VTT termination for address,  
command and control signals  
Motherboard termination to  
VTT for all signals  
VTT termination for address,  
command and control signals  
Same as DDR3  
Same as DDR3  
Not as demanding  
Not as demanding  
Only 34 signals (address,  
command, control) tied to  
VTT  
Only 34 signals (address,  
command, control) tied to  
VTT  
Max source/sink transient  
currents of up to 2.6A to  
2.9A  
Termination  
Current Demand  
ODT handles data signals  
ODT handles data signals  
Less than 1A of burst current  
Less than 1A of burst current  
2.5V Core and I/O 1.25V  
VTT  
1.2V Core and  
I/O 0.6V VTT  
Voltage Level  
1.8V Core and I/O 0.9V VTT  
1.5V Core and I/O 0.75V VTT  
The TPS51200 is designed as a Gm driven LDO. The voltage droop between the reference input and the output  
regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 2 A  
and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very low at no  
load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop is  
only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1) .  
Gm  
F
=
UGBW  
2´ p´ C  
OUT  
(1)  
where  
FUGBW is the unity gain bandwidth  
Gm is transconductance  
COUT is the output capacitance  
There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. In order  
to maintain stablility, the zero location contributed by the ESR of the output capacitors should be greater than the  
-3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the  
design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to  
prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor and  
parasitic inductance of the VO trace.  
12  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS51200