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SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME
DRVH
DRVL
EN_PSV
GND
LL
PGND
PGOOD
TON
TRIP
VBST
VFB
VOUT
V5DRV
V5FILT
NO.
13
9
1
7
12
8
6
2
11
14
5
3
10
4
I/O
O
O
I
I
I/O
I/O
O
I
I
I
I
I
I
I
DESCRIPTION
High-side NFET gate driver output. Source 5
Ω,
sink 1.5
Ω
LL-node referenced driver. Drive voltage
corresponds to VBST to LL voltage.
Rectifying (low-side) NFET gate driver output. Source 5
Ω,
sink 1.5
Ω
PGND referenced driver. Drive voltage
is V5DRV voltage.
Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and
activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode).
Signal ground pin.
High-side NFET gate driver return. Also serves as anode of overcurrent comparator.
Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the
output discharge switch.
Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current
capability is 7.5 mA.
On-time / frequency adjustment pin. Connect to LL with 100-kΩ to 600-kΩ resistor.
Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both
overcurrent and negative overcurrent limit.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An
internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if
forward drop is critical to drive the power NFET.
SMPS voltage feedback input. Connect the resistor divider here for adjustable output.
Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment,
and input for the output discharge switch.
5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1
μF
or
more between this pin and PGND to support instantaneous current for gate drivers.
5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17
mV/μs or less and T
j
< 85°C to secure safe start-up of the internal reference circuit. Apply RC filter consists of
300
Ω
+ 1
μF
or 100
Ω
+ 4.7
μF
at the pin input.
TSSOP (PW) PACKAGE
(TOP VIEW)
QFN (RGY) PACKAGE
(BOTTOM VIEW)
EN_PSV
VBST
EN_PSV
TON
2
3
4
5
6
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VBST
DRVH
LL
TRIP
V5DRV
DRVL
PGND
14
1
DRVH
LL
TRIP
V5DRV
DRVL
13
12
11
10
9
8
7
TON
VOUT
V5FILT
VFB
PGOOD
VOUT
V5FILT
VFB
PGOOD
GND
Copyright © 2005–2009, Texas Instruments Incorporated
PGND
GND
Product Folder Link(s) :TPS51117
5
TI [ TEXAS INSTRUMENTS ]
